diff options
author | Achin Gupta <achin.gupta@arm.com> | 2013-10-25 09:08:21 +0100 |
---|---|---|
committer | James Morrissey <james.morrissey@arm.com> | 2013-10-25 09:37:16 +0100 |
commit | 4f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a56 (patch) | |
tree | 475db5d74370cb62b02afab0900774955a59702f /bl1 | |
download | trusted-firmware-a-4f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a56.tar.gz |
ARMv8 Trusted Firmware release v0.2v0.2
Diffstat (limited to 'bl1')
-rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 83 | ||||
-rw-r--r-- | bl1/aarch64/bl1_entrypoint.S | 93 | ||||
-rw-r--r-- | bl1/aarch64/early_exceptions.S | 216 | ||||
-rw-r--r-- | bl1/bl1.ld.S | 90 | ||||
-rw-r--r-- | bl1/bl1.mk | 46 | ||||
-rw-r--r-- | bl1/bl1_main.c | 132 |
6 files changed, 660 insertions, 0 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c new file mode 100644 index 0000000000..d4be9d6bec --- /dev/null +++ b/bl1/aarch64/bl1_arch_setup.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2013, ARM Limited. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch_helpers.h> +#include <platform.h> +#include <assert.h> + +/******************************************************************************* + * Function that does the first bit of architectural setup that affects + * execution in the non-secure address space. + ******************************************************************************/ +void bl1_arch_setup(void) +{ + unsigned long tmp_reg = 0; + unsigned int counter_base_frequency; + + /* Enable alignment checks and set the exception endianess to LE */ + tmp_reg = read_sctlr(); + tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); + tmp_reg &= ~SCTLR_EE_BIT; + write_sctlr(tmp_reg); + + /* + * Enable HVCs, route FIQs to EL3, set the next EL to be aarch64 + */ + tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_FIQ_BIT; + write_scr(tmp_reg); + + /* Do not trap coprocessor accesses from lower ELs to EL3 */ + write_cptr_el3(0); + + /* Read the frequency from Frequency modes table */ + counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); + /* The first entry of the frequency modes table must not be 0 */ + assert(counter_base_frequency != 0); + + /* Program the counter frequency */ + write_cntfrq_el0(counter_base_frequency); + return; +} + +/******************************************************************************* + * Set the Secure EL1 required architectural state + ******************************************************************************/ +void bl1_arch_next_el_setup(void) { + unsigned long current_sctlr, next_sctlr; + + /* Use the same endianness than the current BL */ + current_sctlr = read_sctlr(); + next_sctlr = (current_sctlr & SCTLR_EE_BIT); + + /* Set SCTLR Secure EL1 */ + next_sctlr |= SCTLR_EL1_RES1; + + write_sctlr_el1(next_sctlr); +} diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S new file mode 100644 index 0000000000..f5ccc65511 --- /dev/null +++ b/bl1/aarch64/bl1_entrypoint.S @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2013, ARM Limited. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + + .globl reset_handler + + + .section reset_code, "ax"; .align 3 + + /* ----------------------------------------------------- + * reset_handler() is the entry point into the trusted + * firmware code when a cpu is released from warm or + * cold reset. + * ----------------------------------------------------- + */ + +reset_handler:; .type reset_handler, %function + /* --------------------------------------------- + * Perform any processor specific actions upon + * reset e.g. cache, tlb invalidations etc. + * --------------------------------------------- + */ + bl cpu_reset_handler + +_wait_for_entrypoint: + /* --------------------------------------------- + * Find the type of reset and jump to handler + * if present. If the handler is null then it is + * a cold boot. The primary cpu will set up the + * platform while the secondaries wait for + * their turn to be woken up + * --------------------------------------------- + */ + bl read_mpidr + bl platform_get_entrypoint + cbnz x0, _do_warm_boot + bl read_mpidr + bl platform_is_primary_cpu + cbnz x0, _do_cold_boot + + /* --------------------------------------------- + * Perform any platform specific secondary cpu + * actions + * --------------------------------------------- + */ + bl plat_secondary_cold_boot_setup + b _wait_for_entrypoint + +_do_cold_boot: + /* --------------------------------------------- + * Initialize platform and jump to our c-entry + * point for this type of reset + * --------------------------------------------- + */ + adr x0, bl1_main + bl platform_cold_boot_init + b _panic + +_do_warm_boot: + /* --------------------------------------------- + * Jump to BL31 for all warm boot init. + * --------------------------------------------- + */ + blr x0 +_panic: + b _panic diff --git a/bl1/aarch64/early_exceptions.S b/bl1/aarch64/early_exceptions.S new file mode 100644 index 0000000000..08a1122514 --- /dev/null +++ b/bl1/aarch64/early_exceptions.S @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2013, ARM Limited. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <arch.h> +#include <bl_common.h> +#include <bl1.h> +#include <platform.h> +#include <runtime_svc.h> + + .globl early_exceptions + + + .section .text, "ax"; .align 11 + + /* ----------------------------------------------------- + * Very simple exception handlers used by BL1 and BL2. + * Apart from one SMC exception all other traps loop + * endlessly. + * ----------------------------------------------------- + */ + .align 7 +early_exceptions: + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x180 + * ----------------------------------------------------- + */ +SynchronousExceptionSP0: + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + b SynchronousExceptionSP0 + + .align 7 +IrqSP0: + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + b IrqSP0 + + .align 7 +FiqSP0: + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + b FiqSP0 + + .align 7 +SErrorSP0: + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + b SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x380 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionSPx: + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + b SynchronousExceptionSPx + + .align 7 +IrqSPx: + mov x0, #IRQ_SP_ELX + bl plat_report_exception + b IrqSPx + + .align 7 +FiqSPx: + mov x0, #FIQ_SP_ELX + bl plat_report_exception + b FiqSPx + + .align 7 +SErrorSPx: + mov x0, #SERROR_SP_ELX + bl plat_report_exception + b SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x580 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA64: + /* --------------------------------------------- + * Only a single SMC exception from BL2 to ask + * BL1 to pass EL3 control to BL31 is expected + * here. + * --------------------------------------------- + */ + sub sp, sp, #0x40 + stp x0, x1, [sp, #0x0] + stp x2, x3, [sp, #0x10] + stp x4, x5, [sp, #0x20] + stp x6, x7, [sp, #0x30] + mov x19, x0 + mov x20, x1 + mov x21, x2 + + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + + bl read_esr + ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x1, #EC_AARCH64_SMC + b.ne panic + mov x1, #RUN_IMAGE + cmp x19, x1 + b.ne panic + mov x0, x20 + mov x1, x21 + mov x2, x3 + mov x3, x4 + bl display_boot_progress + mov x0, x20 + bl write_elr + mov x0, x21 + bl write_spsr + ubfx x0, x21, #MODE_EL_SHIFT, #2 + cmp x0, #MODE_EL3 + b.ne skip_mmu_teardown + /* --------------------------------------------- + * If BL31 is to be executed in EL3 as well + * then turn off the MMU so that it can perform + * its own setup. TODO: Assuming flat mapped + * translations here. Also all should go into a + * separate MMU teardown function + * --------------------------------------------- + */ + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) + bl read_sctlr + bic x0, x0, x1 + bl write_sctlr + mov x0, #DCCISW + bl dcsw_op_all + bl tlbialle3 +skip_mmu_teardown: + ldp x6, x7, [sp, #0x30] + ldp x4, x5, [sp, #0x20] + ldp x2, x3, [sp, #0x10] + ldp x0, x1, [sp, #0x0] + add sp, sp, #0x40 + eret +panic: + b panic + .align 7 +IrqA64: + mov x0, #IRQ_AARCH64 + bl plat_report_exception + b IrqA64 + + .align 7 +FiqA64: + mov x0, #FIQ_AARCH64 + bl plat_report_exception + b FiqA64 + + .align 7 +SErrorA64: + mov x0, #SERROR_AARCH64 + bl plat_report_exception + b SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x0 - 0x180 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA32: + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + b SynchronousExceptionA32 + + .align 7 +IrqA32: + mov x0, #IRQ_AARCH32 + bl plat_report_exception + b IrqA32 + + .align 7 +FiqA32: + mov x0, #FIQ_AARCH32 + bl plat_report_exception + b FiqA32 + + .align 7 +SErrorA32: + mov x0, #SERROR_AARCH32 + bl plat_report_exception + b SErrorA32 diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S new file mode 100644 index 0000000000..5327715559 --- /dev/null +++ b/bl1/bl1.ld.S @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013, ARM Limited. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <platform.h> + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) + +MEMORY { + /* ROM is read-only and executable */ + ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE + /* RAM is read/write and Initialised */ + RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE +} + +SECTIONS +{ + FIRMWARE_ROM : { + *(reset_code) + *(.text) + *(.rodata) + } >ROM + + .bss : { + __BSS_RAM_START__ = .; + *(.bss) + *(COMMON) + __BSS_RAM_STOP__ = .; + } >RAM AT>ROM + + .data : { + __DATA_RAM_START__ = .; + *(.data) + __DATA_RAM_STOP__ = .; + } >RAM AT>ROM + + FIRMWARE_RAM_STACKS ALIGN (PLATFORM_CACHE_LINE_SIZE) : { + . += 0x1000; + *(tzfw_normal_stacks) + . = ALIGN(4096); + } >RAM AT>ROM + + FIRMWARE_RAM_COHERENT ALIGN (4096): { + *(tzfw_coherent_mem) +/* . += 0x1000;*/ +/* Do we need to make sure this is at least 4k? */ + . = ALIGN(4096); + } >RAM + + __FIRMWARE_ROM_START__ = LOADADDR(FIRMWARE_ROM); + __FIRMWARE_ROM_SIZE__ = SIZEOF(FIRMWARE_ROM); + + __FIRMWARE_DATA_START__ = LOADADDR(.data); + __FIRMWARE_DATA_SIZE__ = SIZEOF(.data); + + __FIRMWARE_BSS_START__ = LOADADDR(.bss); + __FIRMWARE_BSS_SIZE__ = SIZEOF(.bss); + + __FIRMWARE_RAM_STACKS_START__ = LOADADDR(FIRMWARE_RAM_STACKS); + __FIRMWARE_RAM_STACKS_SIZE__ = SIZEOF(FIRMWARE_RAM_STACKS); + __FIRMWARE_RAM_COHERENT_START__ = LOADADDR(FIRMWARE_RAM_COHERENT); + __FIRMWARE_RAM_COHERENT_SIZE__ = SIZEOF(FIRMWARE_RAM_COHERENT); +} diff --git a/bl1/bl1.mk b/bl1/bl1.mk new file mode 100644 index 0000000000..b159fd9dde --- /dev/null +++ b/bl1/bl1.mk @@ -0,0 +1,46 @@ +# +# Copyright (c) 2013, ARM Limited. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +vpath %.c drivers/arm/interconnect/cci-400/ plat/fvp \ + plat/fvp/${ARCH} drivers/arm/peripherals/pl011 common/ lib/ \ + lib/semihosting arch/aarch64/ lib/non-semihosting + +vpath %.S arch/${ARCH}/cpu plat/common/aarch64 \ + plat/fvp/${ARCH} lib/semihosting/aarch64 \ + include/ lib/arch/aarch64 + +BL1_ASM_OBJS := bl1_entrypoint.o bl1_plat_helpers.o cpu_helpers.o +BL1_C_OBJS := bl1_main.o cci400.o bl1_plat_setup.o bl1_arch_setup.o \ + fvp_common.o fvp_helpers.o early_exceptions.o +BL1_ENTRY_POINT := reset_handler +BL1_MAPFILE := bl1.map +BL1_LINKERFILE := bl1.ld + +BL1_OBJS := $(BL1_C_OBJS) $(BL1_ASM_OBJS) diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c new file mode 100644 index 0000000000..badda64495 --- /dev/null +++ b/bl1/bl1_main.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2013, ARM Limited. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <stdio.h> +#include <string.h> +#include <assert.h> +#include <arch_helpers.h> +#include <platform.h> +#include <semihosting.h> +#include <bl1.h> + +void bl1_arch_next_el_setup(void); + +/******************************************************************************* + * Function to perform late architectural and platform specific initialization. + * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only + * called by the primary cpu after a cold boot. + * TODO: Add support for alternative image load mechanism e.g using virtio/elf + * loader etc. + ******************************************************************************/ +void bl1_main(void) +{ + unsigned long sctlr_el3 = read_sctlr(); + unsigned long bl2_base; + unsigned int load_type = TOP_LOAD, spsr; + meminfo bl1_tzram_layout, *bl2_tzram_layout = 0x0; + + /* + * Ensure that MMU/Caches and coherency are turned on + */ + assert(sctlr_el3 | SCTLR_M_BIT); + assert(sctlr_el3 | SCTLR_C_BIT); + assert(sctlr_el3 | SCTLR_I_BIT); + + /* Perform remaining generic architectural setup from EL3 */ + bl1_arch_setup(); + + /* Perform platform setup in BL1. */ + bl1_platform_setup(); + + /* Announce our arrival */ + printf(FIRMWARE_WELCOME_STR); + printf("Built : %s, %s\n\r", __TIME__, __DATE__); + + /* + * Find out how much free trusted ram remains after BL1 load + * & load the BL2 image at its top + */ + bl1_tzram_layout = bl1_get_sec_mem_layout(); + bl2_base = load_image(&bl1_tzram_layout, + (const char *) BL2_IMAGE_NAME, + load_type, BL2_BASE); + + /* + * Create a new layout of memory for BL2 as seen by BL1 i.e. + * tell it the amount of total and free memory available. + * This layout is created at the first free address visible + * to BL2. BL2 will read the memory layout before using its + * memory for other purposes. + */ + bl2_tzram_layout = (meminfo *) bl1_tzram_layout.free_base; + init_bl2_mem_layout(&bl1_tzram_layout, + bl2_tzram_layout, + load_type, + bl2_base); + + if (bl2_base) { + bl1_arch_next_el_setup(); + spsr = make_spsr(MODE_EL1, MODE_SP_ELX, MODE_RW_64); + printf("Booting trusted firmware boot loader stage 2\n\r"); +#if DEBUG + printf("BL2 address = 0x%llx \n\r", (unsigned long long) bl2_base); + printf("BL2 cpsr = 0x%x \n\r", spsr); + printf("BL2 memory layout address = 0x%llx \n\r", + (unsigned long long) bl2_tzram_layout); +#endif + run_image(bl2_base, spsr, SECURE, bl2_tzram_layout, 0); + } + + /* + * TODO: print failure to load BL2 but also add a tzwdog timer + * which will reset the system eventually. + */ + printf("Failed to load boot loader stage 2 (BL2) firmware.\n\r"); + return; +} + +/******************************************************************************* + * Temporary function to print the fact that BL2 has done its job and BL31 is + * about to be loaded. This is needed as long as printfs cannot be used + ******************************************************************************/ +void display_boot_progress(unsigned long entrypoint, + unsigned long spsr, + unsigned long mem_layout, + unsigned long ns_image_info) +{ + printf("Booting trusted firmware boot loader stage 3\n\r"); +#if DEBUG + printf("BL31 address = 0x%llx \n\r", (unsigned long long) entrypoint); + printf("BL31 cpsr = 0x%llx \n\r", (unsigned long long)spsr); + printf("BL31 memory layout address = 0x%llx \n\r", (unsigned long long)mem_layout); + printf("BL31 non-trusted image info address = 0x%llx\n\r", (unsigned long long)ns_image_info); +#endif + return; +} |