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author | danh-arm <dan.handley@arm.com> | 2014-05-08 12:01:24 +0100 |
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committer | danh-arm <dan.handley@arm.com> | 2014-05-08 12:01:24 +0100 |
commit | 18a17e6a4a146452dc3fa7dd8ad6aecf3a575e80 (patch) | |
tree | e2047d2ad1b618b9f021cd824ab36ecfd086db06 /bl1 | |
parent | fd6fede5b6183143eaac3c79e2bcfb13c0492dea (diff) | |
parent | 40fd072548ab47ce21bc48dc8059513048693f4e (diff) | |
download | trusted-firmware-a-18a17e6a4a146452dc3fa7dd8ad6aecf3a575e80.tar.gz |
Merge pull request #62 from athoelke/set-little-endian-v2
Set processor endianness immediately after RESET v2
Diffstat (limited to 'bl1')
-rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 3 | ||||
-rw-r--r-- | bl1/aarch64/bl1_entrypoint.S | 10 |
2 files changed, 11 insertions, 2 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index a1ebbdb207..5725bac128 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -39,10 +39,9 @@ void bl1_arch_setup(void) { unsigned long tmp_reg = 0; - /* Enable alignment checks and set the exception endianess to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); isb(); diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index c081af48fe..7259601d15 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -43,6 +43,16 @@ func bl1_entrypoint /* --------------------------------------------- + * Set the CPU endianness before doing anything + * that might involve memory reads or writes + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + + /* --------------------------------------------- * Perform any processor specific actions upon * reset e.g. cache, tlb invalidations etc. * --------------------------------------------- |