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authorAchin Gupta <achin.gupta@arm.com>2014-08-04 23:13:10 +0100
committerAchin Gupta <achin.gupta@arm.com>2014-08-15 10:21:50 +0100
commit0c8d4fef28768233f1f46b4d085f904293dffd2c (patch)
treef921b7d842ce3a7be0e7e701f35fbea187e8dee6 /bl1
parentc1efc4c0666b95912b54e079de484d8c2249e045 (diff)
downloadtrusted-firmware-a-0c8d4fef28768233f1f46b4d085f904293dffd2c.tar.gz
Unmask SError interrupt and clear SCR_EL3.EA bit
This patch disables routing of external aborts from lower exception levels to EL3 and ensures that a SError interrupt generated as a result of execution in EL3 is taken locally instead of a lower exception level. The SError interrupt is enabled in the TSP code only when the operation has not been directly initiated by the normal world. This is to prevent the possibility of an asynchronous external abort which originated in normal world from being taken when execution is in S-EL1. Fixes ARM-software/tf-issues#153 Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
Diffstat (limited to 'bl1')
-rw-r--r--bl1/aarch64/bl1_arch_setup.c13
-rw-r--r--bl1/aarch64/bl1_entrypoint.S8
-rw-r--r--bl1/aarch64/bl1_exceptions.S3
3 files changed, 13 insertions, 11 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c
index eeaa24aff1..6a3f062316 100644
--- a/bl1/aarch64/bl1_arch_setup.c
+++ b/bl1/aarch64/bl1_arch_setup.c
@@ -37,17 +37,8 @@
******************************************************************************/
void bl1_arch_setup(void)
{
- /*
- * Set the next EL to be AArch64, route external abort and SError
- * interrupts to EL3
- */
- write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT | SCR_EA_BIT);
-
- /*
- * Enable SError and Debug exceptions
- */
- enable_serror();
- enable_debug_exceptions();
+ /* Set the next EL to be AArch64 */
+ write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT);
}
/*******************************************************************************
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index dd7d78feb2..e7f92c71dd 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -76,6 +76,14 @@ func bl1_entrypoint
*/
adr x0, bl1_exceptions
msr vbar_el3, x0
+ isb
+
+ /* ---------------------------------------------
+ * Enable the SError interrupt now that the
+ * exception vectors have been setup.
+ * ---------------------------------------------
+ */
+ msr daifclr, #DAIF_ABT_BIT
/* ---------------------------------------------------------------------
* The initial state of the Architectural feature trap register
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 8ab9df8611..13b34b79fa 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -112,6 +112,9 @@ SErrorSPx:
*/
.align 7
SynchronousExceptionA64:
+ /* Enable the SError interrupt */
+ msr daifclr, #DAIF_ABT_BIT
+
/* ------------------------------------------------
* Only a single SMC exception from BL2 to ask
* BL1 to pass EL3 control to BL31 is expected