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authorJavier Almansa Sobrino <javier.almansasobrino@arm.com>2020-11-23 18:38:15 +0000
committerJavier Almansa Sobrino <javier.almansasobrino@arm.com>2020-12-11 12:49:20 +0000
commit0063dd1708e67e5d36168caaf2a0df383bbe1455 (patch)
treed6297557e50a6c6c4672f78b37efa649f4439c74 /bl1
parent852e494075d92199e9bddfe92d364f2107a5a25d (diff)
downloadtrusted-firmware-a-0063dd1708e67e5d36168caaf2a0df383bbe1455.tar.gz
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
Diffstat (limited to 'bl1')
-rw-r--r--bl1/bl1.mk6
1 files changed, 5 insertions, 1 deletions
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index b839990751..d11b4ab0ed 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -16,6 +16,10 @@ BL1_SOURCES += bl1/bl1_main.c \
plat/common/${ARCH}/platform_up_stack.S \
${MBEDTLS_SOURCES}
+ifeq (${DISABLE_MTPMU},1)
+BL1_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
+endif
+
ifeq (${ARCH},aarch64)
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
lib/el3_runtime/aarch64/context.S