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authorSandrine Bailleux <sandrine.bailleux@arm.com>2013-11-12 16:41:16 +0000
committerDan Handley <dan.handley@arm.com>2013-11-27 15:31:06 +0000
commitc10bd2ce69e54a8c71fa773810e130fc465c03ac (patch)
tree34e34f2b4a21a448c4823f8b591579cfd1ca9f36 /bl1/aarch64/bl1_entrypoint.S
parentba3155bb0eb51ca4b5dcf43877c394381cff2fb1 (diff)
downloadtrusted-firmware-a-c10bd2ce69e54a8c71fa773810e130fc465c03ac.tar.gz
Move generic architectural setup out of blx_plat_arch_setup().
blx_plat_arch_setup() should only perform platform-specific architectural setup, e.g. enabling the MMU. This patch moves generic architectural setup code out of blx_plat_arch_setup(). Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6
Diffstat (limited to 'bl1/aarch64/bl1_entrypoint.S')
-rw-r--r--bl1/aarch64/bl1_entrypoint.S18
1 files changed, 18 insertions, 0 deletions
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index f5ccc65511..9db2bdf092 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -28,6 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include <arch.h>
.globl reset_handler
@@ -49,6 +50,23 @@ reset_handler:; .type reset_handler, %function
*/
bl cpu_reset_handler
+ /* ---------------------------------------------
+ * Set the exception vector to something sane.
+ * ---------------------------------------------
+ */
+ adr x0, early_exceptions
+ msr vbar_el3, x0
+
+ /* ---------------------------------------------
+ * Enable the instruction cache.
+ * ---------------------------------------------
+ */
+ mrs x0, sctlr_el3
+ orr x0, x0, #SCTLR_I_BIT
+ msr sctlr_el3, x0
+
+ isb
+
_wait_for_entrypoint:
/* ---------------------------------------------
* Find the type of reset and jump to handler