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authorSoby Mathew <soby.mathew@arm.com>2014-08-14 11:33:56 +0100
committerDan Handley <dan.handley@arm.com>2014-08-20 19:13:25 +0100
commit9b4768417051ead50135d1d7675cab940d864e8d (patch)
tree3105204d317eb7516d184923a8ea66da3aa767f2 /bl1/aarch64/bl1_entrypoint.S
parentaecc0840805672279e4165f4d368a59b5c20771e (diff)
downloadtrusted-firmware-a-9b4768417051ead50135d1d7675cab940d864e8d.tar.gz
Introduce framework for CPU specific operations
This patch introduces a framework which will allow CPUs to perform implementation defined actions after a CPU reset, during a CPU or cluster power down, and when a crash occurs. CPU specific reset handlers have been implemented in this patch. Other handlers will be implemented in subsequent patches. Also moved cpu_helpers.S to the new directory lib/cpus/aarch64/. Change-Id: I1ca1bade4d101d11a898fb30fea2669f9b37b956
Diffstat (limited to 'bl1/aarch64/bl1_entrypoint.S')
-rw-r--r--bl1/aarch64/bl1_entrypoint.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index e7f92c71dd..82330c11eb 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -57,7 +57,7 @@ func bl1_entrypoint
* reset e.g. cache, tlb invalidations etc.
* ---------------------------------------------
*/
- bl cpu_reset_handler
+ bl reset_handler
/* ---------------------------------------------
* Enable the instruction cache, stack pointer