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authorAchin Gupta <achin.gupta@arm.com>2014-06-25 19:26:22 +0100
committerAchin Gupta <achin.gupta@arm.com>2014-07-19 23:31:50 +0100
commit754a2b7a092d3cf81767f1b5a6ab61531792e45f (patch)
tree006669dee127708281859606982fb6b2e59ad8aa /bl1/aarch64/bl1_entrypoint.S
parenta1a441775f64da2cbbd42c4f2c6f818f93278fca (diff)
downloadtrusted-firmware-a-754a2b7a092d3cf81767f1b5a6ab61531792e45f.tar.gz
Remove coherent stack usage from the cold boot path
This patch reworks the cold boot path across the BL1, BL2, BL3-1 and BL3-2 boot loader stages to not use stacks allocated in coherent memory for early platform setup and enabling the MMU. Stacks allocated in normal memory are used instead. Attributes for stack memory change from nGnRnE when the MMU is disabled to Normal WBWA Inner-shareable when the MMU and data cache are enabled. It is possible for the CPU to read stale stack memory after the MMU is enabled from another CPUs cache. Hence, it is unsafe to turn on the MMU and data cache while using normal stacks when multiple CPUs are a part of the same coherency domain. It is safe to do so in the cold boot path as only the primary cpu executes it. The secondary cpus are in a quiescent state. This patch does not remove the allocation of coherent stack memory. That is done in a subsequent patch. Change-Id: I12c80b7c7ab23506d425c5b3a8a7de693498f830
Diffstat (limited to 'bl1/aarch64/bl1_entrypoint.S')
-rw-r--r--bl1/aarch64/bl1_entrypoint.S22
1 files changed, 8 insertions, 14 deletions
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index 50cfae65c4..ac6d91331f 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -130,14 +130,16 @@ func bl1_entrypoint
ldr x2, =__DATA_SIZE__
bl memcpy16
- /* ---------------------------------------------
- * Give ourselves a small coherent stack to
- * ease the pain of initializing the MMU and
- * CCI in assembler
- * ---------------------------------------------
+ /* --------------------------------------------
+ * Allocate a stack whose memory will be marked
+ * as Normal-IS-WBWA when the MMU is enabled.
+ * There is no risk of reading stale stack
+ * memory after enabling the MMU as only the
+ * primary cpu is running at the moment.
+ * --------------------------------------------
*/
mrs x0, mpidr_el1
- bl platform_set_coherent_stack
+ bl platform_set_stack
/* ---------------------------------------------
* Architectural init. can be generic e.g.
@@ -150,14 +152,6 @@ func bl1_entrypoint
bl bl1_early_platform_setup
bl bl1_plat_arch_setup
- /* ---------------------------------------------
- * Give ourselves a stack allocated in Normal
- * -IS-WBWA memory
- * ---------------------------------------------
- */
- mrs x0, mpidr_el1
- bl platform_set_stack
-
/* --------------------------------------------------
* Initialize platform and jump to our c-entry point
* for this type of reset. Panic if it returns