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authorSandrine Bailleux <sandrine.bailleux@arm.com>2015-05-19 11:54:45 +0100
committerSandrine Bailleux <sandrine.bailleux@arm.com>2015-06-04 11:38:54 +0100
commit52010cc779a59f2bc8a23fa5754630a6e63119a4 (patch)
tree500fca98f3a6c1211e2939309c9dfaaa3cbd61b6 /bl1/aarch64/bl1_entrypoint.S
parent452b7fa25ef0381e75a1c066cc2898dd424cabfa (diff)
downloadtrusted-firmware-a-52010cc779a59f2bc8a23fa5754630a6e63119a4.tar.gz
Rationalize reset handling code
The attempt to run the CPU reset code as soon as possible after reset results in highly complex conditional code relating to the RESET_TO_BL31 option. This patch relaxes this requirement a little. In the BL1, BL3-1 and PSCI entrypoints code, the sequence of operations is now as follows: 1) Detect whether it is a cold or warm boot; 2) For cold boot, detect whether it is the primary or a secondary CPU. This is needed to handle multiple CPUs entering cold reset simultaneously; 3) Run the CPU init code. This patch also abstracts the EL3 registers initialisation done by the BL1, BL3-1 and PSCI entrypoints into common code. This improves code re-use and consolidates the code flows for different types of systems. NOTE: THE FUNCTION plat_secondary_cold_boot() IS NOW EXPECTED TO NEVER RETURN. THIS PATCH FORCES PLATFORM PORTS THAT RELIED ON THE FORMER RETRY LOOP AT THE CALL SITE TO MODIFY THEIR IMPLEMENTATION. OTHERWISE, SECONDARY CPUS WILL PANIC. Change-Id: If5ecd74d75bee700b1bd718d23d7556b8f863546
Diffstat (limited to 'bl1/aarch64/bl1_entrypoint.S')
-rw-r--r--bl1/aarch64/bl1_entrypoint.S121
1 files changed, 9 insertions, 112 deletions
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index 8babb33c83..147c930c37 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -29,7 +29,7 @@
*/
#include <arch.h>
-#include <asm_macros.S>
+#include <el3_common_macros.S>
.globl bl1_entrypoint
@@ -42,116 +42,13 @@
*/
func bl1_entrypoint
- /* ---------------------------------------------
- * Set the CPU endianness before doing anything
- * that might involve memory reads or writes.
- * ---------------------------------------------
- */
- mrs x0, sctlr_el3
- bic x0, x0, #SCTLR_EE_BIT
- msr sctlr_el3, x0
- isb
-
- /* ---------------------------------------------
- * Perform any processor specific actions upon
- * reset e.g. cache, tlb invalidations etc.
- * ---------------------------------------------
- */
- bl reset_handler
-
- /* ---------------------------------------------
- * Enable the instruction cache, stack pointer
- * and data access alignment checks
- * ---------------------------------------------
- */
- mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
- mrs x0, sctlr_el3
- orr x0, x0, x1
- msr sctlr_el3, x0
- isb
-
- /* ---------------------------------------------
- * Set the exception vector to something sane.
- * ---------------------------------------------
- */
- adr x0, bl1_exceptions
- msr vbar_el3, x0
- isb
-
- /* ---------------------------------------------
- * Enable the SError interrupt now that the
- * exception vectors have been setup.
- * ---------------------------------------------
- */
- msr daifclr, #DAIF_ABT_BIT
-
- /* ---------------------------------------------------------------------
- * The initial state of the Architectural feature trap register
- * (CPTR_EL3) is unknown and it must be set to a known state. All
- * feature traps are disabled. Some bits in this register are marked as
- * Reserved and should not be modified.
- *
- * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
- * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
- * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
- * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
- * access to trace functionality is not supported, this bit is RES0.
- * CPTR_EL3.TFP: This causes instructions that access the registers
- * associated with Floating Point and Advanced SIMD execution to trap
- * to EL3 when executed from any exception level, unless trapped to EL1
- * or EL2.
- * ---------------------------------------------------------------------
- */
- mrs x0, cptr_el3
- bic w0, w0, #TCPAC_BIT
- bic w0, w0, #TTA_BIT
- bic w0, w0, #TFP_BIT
- msr cptr_el3, x0
-
- /* -------------------------------------------------------
- * Will not return from this macro if it is a warm boot.
- * -------------------------------------------------------
- */
- wait_for_entrypoint
-
- bl platform_mem_init
-
- /* ---------------------------------------------
- * Init C runtime environment.
- * - Zero-initialise the NOBITS sections.
- * There are 2 of them:
- * - the .bss section;
- * - the coherent memory section.
- * - Copy the data section from BL1 image
- * (stored in ROM) to the correct location
- * in RAM.
- * ---------------------------------------------
- */
- ldr x0, =__BSS_START__
- ldr x1, =__BSS_SIZE__
- bl zeromem16
-
-#if USE_COHERENT_MEM
- ldr x0, =__COHERENT_RAM_START__
- ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
- bl zeromem16
-#endif
-
- ldr x0, =__DATA_RAM_START__
- ldr x1, =__DATA_ROM_START__
- ldr x2, =__DATA_SIZE__
- bl memcpy16
-
- /* --------------------------------------------
- * Allocate a stack whose memory will be marked
- * as Normal-IS-WBWA when the MMU is enabled.
- * There is no risk of reading stale stack
- * memory after enabling the MMU as only the
- * primary cpu is running at the moment.
- * --------------------------------------------
- */
- mrs x0, mpidr_el1
- bl platform_set_stack
+ el3_entrypoint_common \
+ _set_endian=1 \
+ _warm_boot_mailbox=1 \
+ _secondary_cold_boot=1 \
+ _init_memory=1 \
+ _init_c_runtime=1 \
+ _exception_vectors=bl1_exceptions
/* ---------------------------------------------
* Architectural init. can be generic e.g.