path: root/bl1/aarch64/bl1_entrypoint.S
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authorAchin Gupta <achin.gupta@arm.com>2014-08-04 23:13:10 +0100
committerAchin Gupta <achin.gupta@arm.com>2014-08-15 10:21:50 +0100
commit0c8d4fef28768233f1f46b4d085f904293dffd2c (patch)
treef921b7d842ce3a7be0e7e701f35fbea187e8dee6 /bl1/aarch64/bl1_entrypoint.S
parentc1efc4c0666b95912b54e079de484d8c2249e045 (diff)
Unmask SError interrupt and clear SCR_EL3.EA bit
This patch disables routing of external aborts from lower exception levels to EL3 and ensures that a SError interrupt generated as a result of execution in EL3 is taken locally instead of a lower exception level. The SError interrupt is enabled in the TSP code only when the operation has not been directly initiated by the normal world. This is to prevent the possibility of an asynchronous external abort which originated in normal world from being taken when execution is in S-EL1. Fixes ARM-software/tf-issues#153 Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
Diffstat (limited to 'bl1/aarch64/bl1_entrypoint.S')
1 files changed, 8 insertions, 0 deletions
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index dd7d78feb2..e7f92c71dd 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -76,6 +76,14 @@ func bl1_entrypoint
adr x0, bl1_exceptions
msr vbar_el3, x0
+ isb
+ /* ---------------------------------------------
+ * Enable the SError interrupt now that the
+ * exception vectors have been setup.
+ * ---------------------------------------------
+ */
+ msr daifclr, #DAIF_ABT_BIT
/* ---------------------------------------------------------------------
* The initial state of the Architectural feature trap register