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authorYann Gautier <yann.gautier@st.com>2020-10-05 11:02:54 +0200
committerYann Gautier <yann.gautier@foss.st.com>2021-04-21 15:05:57 +0200
commit4324a14bf548f5c56edc48128aba1aca0da2edf5 (patch)
tree04388b3318cc52a2109733f20ace432f3a653a6e /bl1/aarch32/bl1_entrypoint.S
parentfb4f511f9b454ea9e03f6391790693a834d8a830 (diff)
downloadtrusted-firmware-a-4324a14bf548f5c56edc48128aba1aca0da2edf5.tar.gz
Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'bl1/aarch32/bl1_entrypoint.S')
-rw-r--r--bl1/aarch32/bl1_entrypoint.S5
1 files changed, 3 insertions, 2 deletions
diff --git a/bl1/aarch32/bl1_entrypoint.S b/bl1/aarch32/bl1_entrypoint.S
index 6a155660b6..94dfd37382 100644
--- a/bl1/aarch32/bl1_entrypoint.S
+++ b/bl1/aarch32/bl1_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,8 @@ func bl1_entrypoint
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl1_vector_table
+ _exception_vectors=bl1_vector_table \
+ _pie_fixup_size=0
/* -----------------------------------------------------
* Perform BL1 setup