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authorDavid Cunado <david.cunado@arm.com>2017-04-13 22:38:29 +0100
committerDavid Cunado <david.cunado@arm.com>2017-06-21 17:57:54 +0100
commit18f2efd67d881fe0a9a535ce9e801e60d746e024 (patch)
tree5c02488f3d5e7c29035e51f65fbe8b83fad74026 /bl1/aarch32/bl1_entrypoint.S
parentb1187232fdf819586ba8c8ece4a27a7515cbdc6d (diff)
downloadtrusted-firmware-a-18f2efd67d881fe0a9a535ce9e801e60d746e024.tar.gz
Fully initialise essential control registers
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
Diffstat (limited to 'bl1/aarch32/bl1_entrypoint.S')
-rw-r--r--bl1/aarch32/bl1_entrypoint.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/bl1/aarch32/bl1_entrypoint.S b/bl1/aarch32/bl1_entrypoint.S
index 39ebcf73d9..778062697e 100644
--- a/bl1/aarch32/bl1_entrypoint.S
+++ b/bl1/aarch32/bl1_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,7 +44,7 @@ func bl1_entrypoint
* ---------------------------------------------------------------------
*/
el3_entrypoint_common \
- _set_endian=1 \
+ _init_sctlr=1 \
_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \