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authorManish Pandey <manish.pandey2@arm.com>2019-11-26 11:34:17 +0000
committerManish Pandey <manish.pandey2@arm.com>2019-12-12 14:16:14 +0000
commitda90359b7852e13dc21f54f4d42df6d4790fe0cd (patch)
treeb3ff7f9b3b9a2828364e9527d3a6c1dac2537176
parentb3257a3d39971663caf4da00b590958264ec46f8 (diff)
downloadtrusted-firmware-a-da90359b7852e13dc21f54f4d42df6d4790fe0cd.tar.gz
PIE: make call to GDT relocation fixup generalized
When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead806 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
-rw-r--r--bl1/aarch64/bl1_entrypoint.S3
-rw-r--r--bl2/aarch64/bl2_el3_entrypoint.S3
-rw-r--r--bl31/aarch64/bl31_entrypoint.S20
-rw-r--r--include/arch/aarch64/el3_common_macros.S29
4 files changed, 38 insertions, 17 deletions
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index 855add347f..00f27184df 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -30,7 +30,8 @@ func bl1_entrypoint
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl1_exceptions
+ _exception_vectors=bl1_exceptions \
+ _pie_fixup_size=0
/* --------------------------------------------------------------------
* Perform BL1 setup
diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S
index 6fe2dd9233..f97121ef01 100644
--- a/bl2/aarch64/bl2_el3_entrypoint.S
+++ b/bl2/aarch64/bl2_el3_entrypoint.S
@@ -26,7 +26,8 @@ func bl2_entrypoint
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl2_el3_exceptions
+ _exception_vectors=bl2_el3_exceptions \
+ _pie_fixup_size=0
/* ---------------------------------------------
* Restore parameters of boot rom
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 1ad26e4fee..74b0993f3a 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -32,17 +32,6 @@ func bl31_entrypoint
mov x22, x2
mov x23, x3
- /* --------------------------------------------------------------------
- * If PIE is enabled, fixup the Global descriptor Table and dynamic
- * relocations
- * --------------------------------------------------------------------
- */
-#if ENABLE_PIE
- mov_imm x0, BL31_BASE
- mov_imm x1, BL31_LIMIT
- bl fixup_gdt_reloc
-#endif /* ENABLE_PIE */
-
#if !RESET_TO_BL31
/* ---------------------------------------------------------------------
* For !RESET_TO_BL31 systems, only the primary CPU ever reaches
@@ -59,7 +48,8 @@ func bl31_entrypoint
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=1 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
#else
/* ---------------------------------------------------------------------
@@ -74,7 +64,8 @@ func bl31_entrypoint
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
/* ---------------------------------------------------------------------
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
@@ -174,7 +165,8 @@ func bl31_warm_entrypoint
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=0 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=0
/*
* We're about to enable MMU and participate in PSCI state coordination.
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 378e827ce1..b14b7b66e3 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -232,11 +232,18 @@
*
* _exception_vectors:
* Address of the exception vectors to program in the VBAR_EL3 register.
+ *
+ * _pie_fixup_size:
+ * Size of memory region to fixup Global Descriptor Table (GDT).
+ *
+ * A non-zero value is expected when firmware needs GDT to be fixed-up.
+ *
* -----------------------------------------------------------------------------
*/
.macro el3_entrypoint_common \
_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
- _init_memory, _init_c_runtime, _exception_vectors
+ _init_memory, _init_c_runtime, _exception_vectors, \
+ _pie_fixup_size
.if \_init_sctlr
/* -------------------------------------------------------------
@@ -283,6 +290,26 @@
do_cold_boot:
.endif /* _warm_boot_mailbox */
+ .if \_pie_fixup_size
+#if ENABLE_PIE
+ /*
+ * ------------------------------------------------------------
+ * If PIE is enabled fixup the Global descriptor Table only
+ * once during primary core cold boot path.
+ *
+ * Compile time base address, required for fixup, is calculated
+ * using "pie_fixup" label present within first page.
+ * ------------------------------------------------------------
+ */
+ pie_fixup:
+ ldr x0, =pie_fixup
+ and x0, x0, #~(PAGE_SIZE - 1)
+ mov_imm x1, \_pie_fixup_size
+ add x1, x1, x0
+ bl fixup_gdt_reloc
+#endif /* ENABLE_PIE */
+ .endif /* _pie_fixup_size */
+
/* ---------------------------------------------------------------------
* Set the exception vectors.
* ---------------------------------------------------------------------