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authorMark Dykes <mark.dykes@arm.com>2021-10-14 22:56:15 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-10-14 22:56:15 +0200
commitd20d5002f9cb1d2711ca02376d94074b561cdf6e (patch)
treeabb9fe8b2fa11cbe574f05f33225c2a64590f4a2
parent34ddd83bc80d102d614299471cb497266a61c69a (diff)
parentb8fe48b6f2b07fce49363cb3c0f8dac9e286439b (diff)
downloadtrusted-firmware-a-d20d5002f9cb1d2711ca02376d94074b561cdf6e.tar.gz
Merge "fix(stm32mp1_clk): fix MCU/AXI parent clock" into integration
-rw-r--r--drivers/st/clk/stm32mp1_clk.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 80b6408e43..d1fc57827a 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -467,12 +467,12 @@ static const uint8_t fmc_parents[] = {
_ACLK, _PLL3_R, _PLL4_P, _CK_PER
};
-static const uint8_t ass_parents[] = {
- _HSI, _HSE, _PLL2
+static const uint8_t axiss_parents[] = {
+ _HSI, _HSE, _PLL2_P
};
-static const uint8_t mss_parents[] = {
- _HSI, _HSE, _CSI, _PLL3
+static const uint8_t mcuss_parents[] = {
+ _HSI, _HSE, _CSI, _PLL3_P
};
static const uint8_t usbphy_parents[] = {
@@ -514,8 +514,8 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
_CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
_CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
_CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
- _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents),
- _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents),
+ _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents),
+ _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents),
_CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
_CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
};