diff options
author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2020-12-23 19:17:18 +0000 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-12-23 19:17:18 +0000 |
commit | c390ecd6db5fadb054466a8d4168d9bbbff2fa95 (patch) | |
tree | 118cb375d3a8bbc5749bc545237526ebc0257eef | |
parent | db7571a2e655755ee7b93903c9dd6275a21730cd (diff) | |
parent | 84af89563e1b17def844d3672bc601ae51f0257f (diff) | |
download | trusted-firmware-a-c390ecd6db5fadb054466a8d4168d9bbbff2fa95.tar.gz |
Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration
* changes:
ti: k3: Introduce lite device board support
ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition
ti: k3: Move USE_COHERENT_MEM only for the generic board
ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain
ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
ti: k3: common: Enable A72 erratum 1319367
ti: k3: common: Enable A53 erratum 1530924
maintainers: Update maintainers for TI port
-rw-r--r-- | docs/about/maintainers.rst | 5 | ||||
-rw-r--r-- | plat/ti/k3/board/generic/board.mk | 7 | ||||
-rw-r--r-- | plat/ti/k3/board/lite/board.mk | 24 | ||||
-rw-r--r-- | plat/ti/k3/board/lite/include/board_def.h | 34 | ||||
-rw-r--r-- | plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c | 14 | ||||
-rw-r--r-- | plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h | 15 | ||||
-rw-r--r-- | plat/ti/k3/common/drivers/ti_sci/ti_sci.c | 1 | ||||
-rw-r--r-- | plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h | 3 | ||||
-rw-r--r-- | plat/ti/k3/common/k3_bl31_setup.c | 34 | ||||
-rw-r--r-- | plat/ti/k3/common/plat_common.mk | 5 | ||||
-rw-r--r-- | plat/ti/k3/include/platform_def.h | 18 |
11 files changed, 154 insertions, 6 deletions
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index f500938842..91a5621b99 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst @@ -516,8 +516,8 @@ Synquacer platform port Texas Instruments platform port ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:M: Andrew F. Davis <afd@ti.com> -:G: `glneo`_ +:M: Nishanth Menon <nm@ti.com> +:G: `nmenon`_ :F: docs/plat/ti-k3.rst :F: plat/ti/ @@ -651,5 +651,6 @@ Build system .. _john-powell-arm: https://github.com/john-powell-arm .. _raghuncstate: https://github.com/raghuncstate .. _CJKay: https://github.com/cjkay +.. _nmenon: https://github.com/nmenon .. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ diff --git a/plat/ti/k3/board/generic/board.mk b/plat/ti/k3/board/generic/board.mk index a342214540..ef74cd64ca 100644 --- a/plat/ti/k3/board/generic/board.mk +++ b/plat/ti/k3/board/generic/board.mk @@ -13,5 +13,12 @@ $(eval $(call add_define,PRELOADED_BL33_BASE)) K3_HW_CONFIG_BASE ?= 0x82000000 $(eval $(call add_define,K3_HW_CONFIG_BASE)) +# Define sec_proxy usage as the full prioritized communication scheme +K3_SEC_PROXY_LITE := 0 +$(eval $(call add_define,K3_SEC_PROXY_LITE)) + +# System coherency is managed in hardware +USE_COHERENT_MEM := 1 + PLAT_INCLUDES += \ -Iplat/ti/k3/board/generic/include \ diff --git a/plat/ti/k3/board/lite/board.mk b/plat/ti/k3/board/lite/board.mk new file mode 100644 index 0000000000..76246be47c --- /dev/null +++ b/plat/ti/k3/board/lite/board.mk @@ -0,0 +1,24 @@ +# +# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BL32_BASE ?= 0x9e800000 +$(eval $(call add_define,BL32_BASE)) + +PRELOADED_BL33_BASE ?= 0x80080000 +$(eval $(call add_define,PRELOADED_BL33_BASE)) + +K3_HW_CONFIG_BASE ?= 0x82000000 +$(eval $(call add_define,K3_HW_CONFIG_BASE)) + +# Define sec_proxy usage as the lite version +K3_SEC_PROXY_LITE := 1 +$(eval $(call add_define,K3_SEC_PROXY_LITE)) + +# We dont have system level coherency capability +USE_COHERENT_MEM := 0 + +PLAT_INCLUDES += \ + -Iplat/ti/k3/board/lite/include \ diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h new file mode 100644 index 0000000000..7c7ea62c10 --- /dev/null +++ b/plat/ti/k3/board/lite/include/board_def.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_DEF_H +#define BOARD_DEF_H + +#include <lib/utils_def.h> + +/* The ports must be in order and contiguous */ +#define K3_CLUSTER0_CORE_COUNT U(4) +#define K3_CLUSTER1_CORE_COUNT U(0) +#define K3_CLUSTER2_CORE_COUNT U(0) +#define K3_CLUSTER3_CORE_COUNT U(0) + +/* + * This RAM will be used for the bootloader including code, bss, and stacks. + * It may need to be increased if BL31 grows in size. + * Current computation assumes data structures necessary for GIC and ARM for + * a single cluster of 4 processor. + */ +#define SEC_SRAM_BASE 0x70000000 /* Base of SRAM */ +#define SEC_SRAM_SIZE 0x0001a000 /* 104k */ + +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_RET_STATE U(1) + +#define PLAT_PROC_START_ID 32 +#define PLAT_PROC_DEVICE_START_ID 135 +#define PLAT_CLUSTER_DEVICE_START_ID 134 + +#endif /* BOARD_DEF_H */ diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c index ee1eecf789..a0bfdee367 100644 --- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c +++ b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c @@ -97,11 +97,16 @@ static struct k3_sec_proxy_mbox spm = { .data_end_offset = 0x3C, }, .threads = { +#if !K3_SEC_PROXY_LITE SP_THREAD(SP_NOTIFY), SP_THREAD(SP_RESPONSE), SP_THREAD(SP_HIGH_PRIORITY), SP_THREAD(SP_LOW_PRIORITY), SP_THREAD(SP_NOTIFY_RESP), +#else + SP_THREAD(SP_RESPONSE), + SP_THREAD(SP_HIGH_PRIORITY), +#endif /* K3_SEC_PROXY_LITE */ }, }; @@ -261,9 +266,14 @@ int k3_sec_proxy_send(enum k3_sec_proxy_chan_id id, const struct k3_sec_proxy_ms /* * 'data_reg' indicates next register to write. If we did not already * write on tx complete reg(last reg), we must do so for transmit + * In addition, we also need to make sure all intermediate data + * registers(if any required), are reset to 0 for TISCI backward + * compatibility to be maintained. */ - if (data_reg <= spm.desc.data_end_offset) - mmio_write_32(spt->data + spm.desc.data_end_offset, 0); + while (data_reg <= spm.desc.data_end_offset) { + mmio_write_32(spt->data + data_reg, 0); + data_reg += sizeof(uint32_t); + } VERBOSE("Message successfully sent on thread %s\n", spt->name); diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h index 6c4f5dfffa..f4b0b4bace 100644 --- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h +++ b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h @@ -16,13 +16,28 @@ * enum k3_sec_proxy_chan_id - Secure Proxy thread IDs * * These the available IDs used in k3_sec_proxy_{send,recv}() + * There are two schemes we use: + * * if K3_SEC_PROXY_LITE = 1, we just have two threads to talk + * * if K3_SEC_PROXY_LITE = 0, we have the full fledged + * communication scheme available. */ enum k3_sec_proxy_chan_id { +#if !K3_SEC_PROXY_LITE SP_NOTIFY = 0, SP_RESPONSE, SP_HIGH_PRIORITY, SP_LOW_PRIORITY, SP_NOTIFY_RESP, +#else + SP_RESPONSE = 8, + /* + * Note: TISCI documentation indicates "low priority", but in reality + * with a single thread, there is no low or high priority.. This usage + * is more appropriate for TF-A since we can reduce the churn as a + * result. + */ + SP_HIGH_PRIORITY, +#endif /* K3_SEC_PROXY_LITE */ }; /** diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c index e390efee6c..2c3313c43e 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c @@ -1163,6 +1163,7 @@ int ti_sci_core_reboot(void) ERROR("Message alloc failed (%d)\n", ret); return ret; } + req.domain = TI_SCI_DOMAIN_FULL_SOC_RESET; ret = ti_sci_do_xfer(&xfer); if (ret) { diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h index 2d23f9a9cf..310bf459d2 100644 --- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h +++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h @@ -95,12 +95,15 @@ struct ti_sci_msg_resp_version { /** * struct ti_sci_msg_req_reboot - Reboot the SoC * @hdr: Generic Header + * @domain: Domain to be reset, 0 for full SoC reboot * * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic * ACK/NACK message. */ struct ti_sci_msg_req_reboot { struct ti_sci_msg_hdr hdr; +#define TI_SCI_DOMAIN_FULL_SOC_RESET 0x0 + uint8_t domain; } __packed; /** diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c index 8bd7362923..ac4e60e4d1 100644 --- a/plat/ti/k3/common/k3_bl31_setup.c +++ b/plat/ti/k3/common/k3_bl31_setup.c @@ -13,6 +13,7 @@ #include <arch_helpers.h> #include <common/bl_common.h> #include <common/debug.h> +#include <lib/mmio.h> #include <lib/xlat_tables/xlat_tables_v2.h> #include <k3_console.h> @@ -23,6 +24,7 @@ const mmap_region_t plat_k3_mmap[] = { MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE), MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE), @@ -127,6 +129,38 @@ void platform_mem_init(void) unsigned int plat_get_syscnt_freq2(void) { + uint32_t gtc_freq; + uint32_t gtc_ctrl; + + /* Lets try and provide basic diagnostics - cost is low */ + gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET); + /* Did the bootloader fail to enable timer and OS guys are confused? */ + if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) { + ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n"); + } + /* + * If debug will not pause time, we will have issues like + * drivers timing out while debugging, in cases of OS like Linux, + * RCU stall errors, which can be hard to differentiate vs real issues. + */ + if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) { + WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n"); + } + + gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET); + /* Many older bootloaders may have missed programming FID0 register */ + if (gtc_freq != 0U) { + return gtc_freq; + } + + /* + * We could have just warned about this, but this can have serious + * hard to debug side effects if we are NOT sure what the actual + * frequency is. Lets make sure people don't miss this. + */ + ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n", + SYS_COUNTER_FREQ_IN_TICKS); + return SYS_COUNTER_FREQ_IN_TICKS; } diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index c00262bcff..ab7366b7e2 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -11,9 +11,8 @@ COLD_BOOT_SINGLE_CPU := 1 # We can choose where a core starts executing PROGRAMMABLE_RESET_ADDRESS:= 1 -# System coherency is managed in hardware +# ARM coherency is managed in hardware WARMBOOT_ENABLE_DCACHE_EARLY := 1 -USE_COHERENT_MEM := 1 # A53 erratum for SoC. (enable them all) ERRATA_A53_826319 := 1 @@ -21,9 +20,11 @@ ERRATA_A53_835769 := 1 ERRATA_A53_836870 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 +ERRATA_A53_1530924 := 1 # A72 Erratum for SoC ERRATA_A72_859971 := 1 +ERRATA_A72_1319367 := 1 CRASH_REPORTING := 1 HANDLE_EA_EL3_FIRST := 1 diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h index 98db626e24..f12fb0b211 100644 --- a/plat/ti/k3/include/platform_def.h +++ b/plat/ti/k3/include/platform_def.h @@ -150,15 +150,33 @@ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_EDGE) + +#define K3_GTC_BASE 0x00A90000 +/* We just need 20 byte offset, but simpler to just remap the 64K page in */ +#define K3_GTC_SIZE 0x10000 +#define K3_GTC_CNTCR_OFFSET 0x00 +#define K3_GTC_CNTCR_EN_MASK 0x01 +#define K3_GTC_CNTCR_HDBG_MASK 0x02 +#define K3_GTC_CNTFID0_OFFSET 0x20 + #define K3_GIC_BASE 0x01800000 #define K3_GIC_SIZE 0x200000 +#if !K3_SEC_PROXY_LITE #define SEC_PROXY_DATA_BASE 0x32C00000 #define SEC_PROXY_DATA_SIZE 0x80000 #define SEC_PROXY_SCFG_BASE 0x32800000 #define SEC_PROXY_SCFG_SIZE 0x80000 #define SEC_PROXY_RT_BASE 0x32400000 #define SEC_PROXY_RT_SIZE 0x80000 +#else +#define SEC_PROXY_DATA_BASE 0x4D000000 +#define SEC_PROXY_DATA_SIZE 0x80000 +#define SEC_PROXY_SCFG_BASE 0x4A400000 +#define SEC_PROXY_SCFG_SIZE 0x80000 +#define SEC_PROXY_RT_BASE 0x4A600000 +#define SEC_PROXY_RT_SIZE 0x80000 +#endif /* K3_SEC_PROXY_LITE */ #define SEC_PROXY_TIMEOUT_US 1000000 #define SEC_PROXY_MAX_MESSAGE_SIZE 56 |