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author | Manish Pandey <manish.pandey2@arm.com> | 2021-01-11 18:22:04 +0000 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2021-01-11 18:22:04 +0000 |
commit | bc0d8c7412389869bc7198ec985ef19966293184 (patch) | |
tree | d288798cf16f67b096e80d49a5181d64f8d18580 | |
parent | f422a7bf5b179be476e97b930fcc25950bf9374b (diff) | |
parent | 240c9cbf15e7c1bbd0d787103fcbfc54df18b80c (diff) | |
download | trusted-firmware-a-bc0d8c7412389869bc7198ec985ef19966293184.tar.gz |
Merge changes I07c35829,Iec7dd019,Ic7406aa8,I4eac94f0 into integration
* changes:
drivers: renesas: rcar: dma: Fix coding style
drivers: renesas: rcar: delay: Fix checkpatch warnings
drivers: renesas: rcar: avs: Fix checkpatch warnings
drivers: renesas: rcar: auth: Use space instead of TAB
-rw-r--r-- | drivers/renesas/rcar/auth/auth_mod.c | 27 | ||||
-rw-r--r-- | drivers/renesas/rcar/avs/avs_driver.c | 74 | ||||
-rw-r--r-- | drivers/renesas/rcar/delay/micro_delay.c | 5 | ||||
-rw-r--r-- | drivers/renesas/rcar/dma/dma_driver.c | 50 |
4 files changed, 81 insertions, 75 deletions
diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/rcar/auth/auth_mod.c index ece3462f45..4aa86e2a4a 100644 --- a/drivers/renesas/rcar/auth/auth_mod.c +++ b/drivers/renesas/rcar/auth/auth_mod.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights * reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -7,29 +7,28 @@ #include <stddef.h> -#include <platform_def.h> - #include <arch_helpers.h> #include <common/debug.h> #include <lib/mmio.h> #include <plat/common/platform.h> +#include <platform_def.h> #include "rom_api.h" typedef int32_t(*secure_boot_api_f) (uint32_t a, uint32_t b, void *c); extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr); -#define RCAR_IMAGE_ID_MAX (10) -#define RCAR_CERT_MAGIC_NUM (0xE291F358U) +#define RCAR_IMAGE_ID_MAX (10) +#define RCAR_CERT_MAGIC_NUM (0xE291F358U) #define RCAR_BOOT_KEY_CERT (0xE6300C00U) #define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U) -#define RST_BASE (0xE6160000U) -#define RST_MODEMR (RST_BASE + 0x0060U) -#define MFISOFTMDR (0xE6260600U) -#define MODEMR_MD5_MASK (0x00000020U) -#define MODEMR_MD5_SHIFT (5U) -#define SOFTMD_BOOTMODE_MASK (0x00000001U) -#define SOFTMD_NORMALBOOT (0x1U) +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) +#define MFISOFTMDR (0xE6260600U) +#define MODEMR_MD5_MASK (0x00000020U) +#define MODEMR_MD5_SHIFT (5U) +#define SOFTMD_BOOTMODE_MASK (0x00000001U) +#define SOFTMD_NORMALBOOT (0x1U) static secure_boot_api_f secure_boot_api; @@ -125,9 +124,9 @@ verify_image: #if RCAR_BL2_DCACHE == 1 /* enable */ write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT); -#endif +#endif /* RCAR_BL2_DCACHE */ -#endif +#endif /* IMAGE_BL2 */ return ret; } diff --git a/drivers/renesas/rcar/avs/avs_driver.c b/drivers/renesas/rcar/avs/avs_driver.c index 647869ede4..2c939cd59a 100644 --- a/drivers/renesas/rcar/avs/avs_driver.c +++ b/drivers/renesas/rcar/avs/avs_driver.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,8 +8,8 @@ #include <lib/mmio.h> #include <lib/utils_def.h> -#include "cpg_registers.h" #include "avs_driver.h" +#include "cpg_registers.h" #include "rcar_def.h" #include "rcar_private.h" @@ -22,12 +22,12 @@ #endif /* PMIC_ROHM_BD9571 */ /* Base address of Adaptive Voltage Scaling module registers*/ -#define AVS_BASE (0xE60A0000U) +#define AVS_BASE (0xE60A0000U) /* Adaptive Dynamic Voltage ADJust Parameter2 registers */ -#define ADVADJP2 (AVS_BASE + 0x013CU) +#define ADVADJP2 (AVS_BASE + 0x013CU) /* Mask VOLCOND bit in ADVADJP2 registers */ -#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */ +#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */ #if PMIC_ROHM_BD9571 /* I2C for DVFS bit in CPG registers for module standby and software reset*/ @@ -38,19 +38,19 @@ #if PMIC_ROHM_BD9571 /* Base address of IICDVFS registers*/ -#define IIC_DVFS_BASE (0xE60B0000U) +#define IIC_DVFS_BASE (0xE60B0000U) /* IIC bus data register */ -#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U) +#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U) /* IIC bus control register */ -#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U) +#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U) /* IIC bus status register */ -#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U) +#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U) /* IIC interrupt control register */ -#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU) +#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU) /* IIC clock control register low */ -#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U) +#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U) /* IIC clock control register high */ -#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U) +#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U) /* Bit in ICSR register */ #define ICSR_BUSY (0x10U) @@ -76,20 +76,23 @@ #define ICCR_STOP_RECV (0xC0U) /* Low-level period of SCL */ -#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */ -#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */ -#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */ -#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */ +#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */ +#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */ +#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */ +#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */ /* High-level period of SCL */ -#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */ -#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */ -#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */ -#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */ +#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */ +#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */ +#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */ +#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */ /* PMIC */ -#define PMIC_W_SLAVE_ADDRESS (0x60U) /* ROHM BD9571 slave address + (W) */ -#define PMIC_R_SLAVE_ADDRESS (0x61U) /* ROHM BD9571 slave address + (R) */ -#define PMIC_DVFS_SETVID (0x54U) /* ROHM BD9571 DVFS SetVID register */ +/* ROHM BD9571 slave address + (W) */ +#define PMIC_W_SLAVE_ADDRESS (0x60U) +/* ROHM BD9571 slave address + (R) */ +#define PMIC_R_SLAVE_ADDRESS (0x61U) +/* ROHM BD9571 DVFS SetVID register */ +#define PMIC_DVFS_SETVID (0x54U) #endif /* PMIC_ROHM_BD9571 */ /* Individual information */ @@ -102,7 +105,7 @@ typedef struct { } initial_voltage_t; static const initial_voltage_t init_vol_tbl[] = { - /* AVS code, RHOM BD9571 DVFS SetVID register */ + /* AVS code, ROHM BD9571 DVFS SetVID register */ {0x00U, 0x53U}, /* AVS0, 0.83V */ {0x01U, 0x52U}, /* AVS1, 0.82V */ {0x02U, 0x51U}, /* AVS2, 0.81V */ @@ -188,7 +191,7 @@ void rcar_avs_init(void) /* Disable I2C module and All internal registers initialized. */ mmio_write_8(IIC_ICCR, 0x00U); while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) { - /* Disable I2C module and All internal registers initialized. */ + /* Disable I2C module and all internal registers initialized. */ mmio_write_8(IIC_ICCR, 0x00U); } @@ -283,8 +286,8 @@ void rcar_avs_setting(void) /* Dose efuse_avs exceed the number of */ /* the tables? */ if (efuse_avs >= EFUSE_AVS_NUM) { - ERROR("AVS number of eFuse is out " - "of a range. number=%u\n", + ERROR("%s%s=%u\n", "AVS number of ", + "eFuse is out of range. number", efuse_avs); /* Infinite loop */ panic(); @@ -417,7 +420,8 @@ void rcar_avs_end(void) { uint8_t addr = PMIC_DVFS_SETVID; uint8_t value = avs_read_pmic_reg(addr); - NOTICE("Read PMIC register. address=0x%x value=0x%x \n", + + NOTICE("Read PMIC register. address=0x%x value=0x%x\n", addr, value); } #endif @@ -446,8 +450,8 @@ static avs_error_t avs_check_error(void) avs_error_t ret; if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) { - NOTICE("Loss of arbitration is detected. " - "AVS status=%d Retry=%u\n", avs_status, avs_retry); + NOTICE("%s AVS status=%d Retry=%u\n", + "Loss of arbitration is detected.", avs_status, avs_retry); /* Check of retry number of times */ if (avs_retry >= AVS_RETRY_NUM) { ERROR("AVS setting failed in retry. max=%u\n", @@ -458,8 +462,8 @@ static avs_error_t avs_check_error(void) /* Set the error detected to error status. */ ret = avs_error_al; } else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) { - NOTICE("Non-acknowledge is detected. " - "AVS status=%d Retry=%u\n", avs_status, avs_retry); + NOTICE("%s AVS status=%d Retry=%u\n", + "Non-acknowledge is detected.", avs_status, avs_retry); /* Check of retry number of times */ if (avs_retry >= AVS_RETRY_NUM) { ERROR("AVS setting failed in retry. max=%u\n", @@ -526,8 +530,10 @@ static uint8_t avs_read_pmic_reg(uint8_t addr) /* Set frequency of 400kHz */ avs_set_iic_clock(); - /* Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission */ - /* interrupt and wait interrupt. */ + /* + * Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission + * interrupt and wait interrupt. + */ mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE); /* Write H'94 in ICCR to issue start condition */ diff --git a/drivers/renesas/rcar/delay/micro_delay.c b/drivers/renesas/rcar/delay/micro_delay.c index aced5891a8..a5e2a69285 100644 --- a/drivers/renesas/rcar/delay/micro_delay.c +++ b/drivers/renesas/rcar/delay/micro_delay.c @@ -1,18 +1,19 @@ /* - * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arch.h> #include <arch_helpers.h> + #include "micro_delay.h" #define RCAR_CONV_MICROSEC 1000000U void #if IMAGE_BL31 - __attribute__ ((section (".system_ram"))) + __attribute__ ((section(".system_ram"))) #endif rcar_micro_delay(uint64_t micro_sec) { diff --git a/drivers/renesas/rcar/dma/dma_driver.c b/drivers/renesas/rcar/dma/dma_driver.c index e0be46e6f9..44ee985923 100644 --- a/drivers/renesas/rcar/dma/dma_driver.c +++ b/drivers/renesas/rcar/dma/dma_driver.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,15 +11,15 @@ #include <common/debug.h> #include <lib/mmio.h> -#include "rcar_def.h" #include "cpg_registers.h" +#include "rcar_def.h" #include "rcar_private.h" /* DMA CHANNEL setting (0/16/32) */ #if RCAR_LSI == RCAR_V3M -#define DMA_CH 16 +#define DMA_CH 16 #else -#define DMA_CH 0 +#define DMA_CH 0 #endif #if (DMA_CH == 0) @@ -39,7 +39,7 @@ /* DMA operation */ #define DMA_DMAOR (DMA_BASE + 0x0060U) /* DMA secure control */ -#define DMA_DMASEC (DMA_BASE + 0x0030U) +#define DMA_DMASEC (DMA_BASE + 0x0030U) /* DMA channel clear */ #define DMA_DMACHCLR (DMA_BASE + 0x0080U) /* DMA source address */ @@ -53,21 +53,21 @@ /* DMA fixed destination address */ #define DMA_DMAFIXDAR (DMA_BASE + 0x8014U) -#define DMA_USE_CHANNEL (0x00000001U) -#define DMAOR_INITIAL (0x0301U) -#define DMACHCLR_CH_ALL (0x0000FFFFU) -#define DMAFIXDAR_32BIT_SHIFT (32U) -#define DMAFIXDAR_DAR_MASK (0x000000FFU) -#define DMADAR_BOUNDARY_ADDR (0x100000000ULL) -#define DMATCR_CNT_SHIFT (6U) -#define DMATCR_MAX (0x00FFFFFFU) -#define DMACHCR_TRN_MODE (0x00105409U) -#define DMACHCR_DE_BIT (0x00000001U) -#define DMACHCR_TE_BIT (0x00000002U) -#define DMACHCR_CHE_BIT (0x80000000U) - -#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT -#define DMA_FRACTION_MASK (0xFFU) +#define DMA_USE_CHANNEL (0x00000001U) +#define DMAOR_INITIAL (0x0301U) +#define DMACHCLR_CH_ALL (0x0000FFFFU) +#define DMAFIXDAR_32BIT_SHIFT (32U) +#define DMAFIXDAR_DAR_MASK (0x000000FFU) +#define DMADAR_BOUNDARY_ADDR (0x100000000ULL) +#define DMATCR_CNT_SHIFT (6U) +#define DMATCR_MAX (0x00FFFFFFU) +#define DMACHCR_TRN_MODE (0x00105409U) +#define DMACHCR_DE_BIT (0x00000001U) +#define DMACHCR_TE_BIT (0x00000002U) +#define DMACHCR_CHE_BIT (0x80000000U) + +#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT +#define DMA_FRACTION_MASK (0xFFU) #define DMA_DST_LIMIT (0x10000000000ULL) /* transfer length limit */ @@ -129,16 +129,16 @@ void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len) } if (src & DMA_FRACTION_MASK) { - ERROR("BL2: DMA - source address invalid (0x%x), " - "length (0x%x)\n", src, dma_len); + ERROR("BL2: DMA - src address invalid (0x%x), len=(0x%x)\n", + src, dma_len); panic(); } if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR || - (dst + dma_len > DMA_DST_LIMIT) || + (dst + dma_len > DMA_DST_LIMIT) || (dst & DMA_FRACTION_MASK)) { - ERROR("BL2: DMA - destination address invalid (0x%lx), " - "length (0x%x)\n", dst, dma_len); + ERROR("BL2: DMA - dest address invalid (0x%lx), len=(0x%x)\n", + dst, dma_len); panic(); } |