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authorHadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>2019-08-16 11:08:14 +0800
committerHadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>2019-08-19 10:56:31 +0800
commit960a12b3fb4699cad83973c853fb5064ed6a75d0 (patch)
tree6a33c0a28c429705fcc976f2addae8c758dc8098
parentd1b6013d8485094d948e6b6039b8d119a907ecf8 (diff)
downloadtrusted-firmware-a-960a12b3fb4699cad83973c853fb5064ed6a75d0.tar.gz
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
-rw-r--r--plat/intel/soc/agilex/include/agilex_clock_manager.h3
-rw-r--r--plat/intel/soc/agilex/soc/agilex_clock_manager.c10
2 files changed, 13 insertions, 0 deletions
diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h
index 73e6c4e19a..0822290aa0 100644
--- a/plat/intel/soc/agilex/include/agilex_clock_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h
@@ -33,6 +33,7 @@
#define CLKMGR_MAINPLL_PLLC2 0x40
#define CLKMGR_MAINPLL_PLLC3 0x44
#define CLKMGR_MAINPLL_PLLM 0x48
+#define CLKMGR_MAINPLL_LOSTLOCK 0x54
/* Peripheral PLL Group */
#define CLKMGR_PERPLL 0xffd1007c
@@ -50,6 +51,7 @@
#define CLKMGR_PERPLL_PLLC2 0x3c
#define CLKMGR_PERPLL_PLLC3 0x40
#define CLKMGR_PERPLL_PLLM 0x44
+#define CLKMGR_PERPLL_LOSTLOCK 0x50
/* Altera Group */
#define CLKMGR_ALTERA 0xffd100d0
@@ -112,6 +114,7 @@
#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
+#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000
typedef struct {
uint32_t clk_freq_of_eosc1;
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 218676a98f..06891ff936 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -222,6 +222,16 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
mmio_write_32(CLKMGR_ALTERA + CLKMGR_ALTERA_PSIREFCTR,
hoff_ptr->alt_psirefctr);
+ /* Clear lost lock bypass mode */
+ mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_LOSTLOCK, 0x1);
+ mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_LOSTLOCK, 0x1);
+
+ mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_CLR_LOSTLOCK_BYPASS);
+
+ mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_CLR_LOSTLOCK_BYPASS);
+
/* Take all PLLs out of bypass */
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0);
wait_fsm();