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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-26 20:04:28 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2019-07-31 16:35:29 +0900 |
commit | 4dd4bde4b7c0db6d5431e942968a71a329286695 (patch) | |
tree | e1e0d35b106d040bb11f949f0e39c632878aad5c | |
parent | f5de1aba3327fec6b15061390a0d40e01ff93df1 (diff) | |
download | trusted-firmware-a-4dd4bde4b7c0db6d5431e942968a71a329286695.tar.gz |
uniphier: fix typo and coding style
Fix the typo "warn" -> "warm".
Also fix the following checkpatch.pl warnings:
CHECK: Prefer using the BIT macro
CHECK: No space is necessary after a cast
CHECK: Alignment should match open parenthesis
CHECK: Unnecessary parentheses around uniphier_io_policies[image_id].dev_handle
Change-Id: Ic11eea2668c4bf2d1e8f089e6338ba7b7156d80b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-rw-r--r-- | plat/socionext/uniphier/uniphier_bl31_setup.c | 4 | ||||
-rw-r--r-- | plat/socionext/uniphier/uniphier_gicv3.c | 20 | ||||
-rw-r--r-- | plat/socionext/uniphier/uniphier_io_storage.c | 4 | ||||
-rw-r--r-- | plat/socionext/uniphier/uniphier_psci.c | 8 |
4 files changed, 18 insertions, 18 deletions
diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c index bf78a14583..440e6aa113 100644 --- a/plat/socionext/uniphier/uniphier_bl31_setup.c +++ b/plat/socionext/uniphier/uniphier_bl31_setup.c @@ -35,7 +35,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { void *from_bl2; - from_bl2 = (void *) arg0; + from_bl2 = (void *)arg0; bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head; @@ -76,7 +76,7 @@ void bl31_platform_setup(void) /* Enable and initialize the System level generic timer */ mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF, - CNTCR_FCREQ(0U) | CNTCR_EN); + CNTCR_FCREQ(0U) | CNTCR_EN); } void bl31_plat_arch_setup(void) diff --git a/plat/socionext/uniphier/uniphier_gicv3.c b/plat/socionext/uniphier/uniphier_gicv3.c index 5148e8f910..266efe7bc9 100644 --- a/plat/socionext/uniphier/uniphier_gicv3.c +++ b/plat/socionext/uniphier/uniphier_gicv3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,34 +21,34 @@ static const interrupt_prop_t uniphier_interrupt_props[] = { /* SGI0 */ INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI6 */ INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* G1S interrupts */ /* Timer */ INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_LEVEL), + GIC_INTR_CFG_LEVEL), /* SGI1 */ INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI2 */ INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI3 */ INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI4 */ INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI5 */ INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE), + GIC_INTR_CFG_EDGE), /* SGI7 */ INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S, - GIC_INTR_CFG_EDGE) + GIC_INTR_CFG_EDGE) }; static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr) diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c index 451e84f9e0..b456bc538b 100644 --- a/plat/socionext/uniphier/uniphier_io_storage.c +++ b/plat/socionext/uniphier/uniphier_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -331,7 +331,7 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, assert(image_id < ARRAY_SIZE(uniphier_io_policies)); - *dev_handle = *(uniphier_io_policies[image_id].dev_handle); + *dev_handle = *uniphier_io_policies[image_id].dev_handle; *image_spec = uniphier_io_policies[image_id].image_spec; init_params = uniphier_io_policies[image_id].init_params; diff --git a/plat/socionext/uniphier/uniphier_psci.c b/plat/socionext/uniphier/uniphier_psci.c index ce11aa7cbb..464252ddd4 100644 --- a/plat/socionext/uniphier/uniphier_psci.c +++ b/plat/socionext/uniphier/uniphier_psci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ #define UNIPHIER_ROM_RSV0 0x59801200 #define UNIPHIER_SLFRSTSEL 0x61843010 -#define UNIPHIER_SLFRSTSEL_MASK (0x3 << 0) +#define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0) #define UNIPHIER_SLFRSTCTL 0x61843014 -#define UNIPHIER_SLFRSTCTL_RST (1 << 0) +#define UNIPHIER_SLFRSTCTL_RST BIT(0) #define MPIDR_AFFINITY_INVALID ((u_register_t)-1) @@ -58,7 +58,7 @@ static void __dead2 uniphier_psci_pwr_domain_pwr_down_wfi( const psci_power_state_t *target_state) { /* - * The Boot ROM cannot distinguish warn and cold resets. + * The Boot ROM cannot distinguish warm and cold resets. * Instead of the CPU reset, fake it. */ uniphier_holding_pen_release = MPIDR_AFFINITY_INVALID; |