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authorMadhukar Pappireddy <madhukar.pappireddy@arm.com>2022-05-19 21:11:55 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2022-05-19 21:11:55 +0200
commit4cafcc30ed9be5a7a55e993ef7148a3bbed395cc (patch)
tree2dbc7dfc6a86b74289981a5ab0915adb99621956
parent70313d363b3a3b8f78cbe2203f36415a1fac5c59 (diff)
parentf1cbbd6332bb85672dc72cbcc4ac7023323c6936 (diff)
downloadtrusted-firmware-a-4cafcc30ed9be5a7a55e993ef7148a3bbed395cc.tar.gz
Merge "fix(bl1): invalidate SP in data cache during secure SMC" into integration
-rw-r--r--bl1/aarch32/bl1_exceptions.S10
1 files changed, 9 insertions, 1 deletions
diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S
index 493d2ca4e5..4a6815f1f1 100644
--- a/bl1/aarch32/bl1_exceptions.S
+++ b/bl1/aarch32/bl1_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -118,6 +118,14 @@ func smc_handler
mov r0, #DISABLE_DCACHE
bl enable_mmu_svc_mon
+ /*
+ * Invalidate `smc_ctx_t` in data cache to prevent dirty data being
+ * used.
+ */
+ mov r0, r6
+ mov r1, #SMC_CTX_SIZE
+ bl inv_dcache_range
+
/* Enable the data cache. */
ldcopr r9, SCTLR
orr r9, r9, #SCTLR_C_BIT