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authorMark Dykes <mardyk01@review.trustedfirmware.org>2020-05-28 18:14:33 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2020-05-28 18:14:33 +0000
commit48b6f1783a1f2ebfe1ec66f1905e36e95bdcab15 (patch)
treeb688d7e1408139a16fa9e5693d26d2f94e2cc070
parent9b9c1f3d607313f0fc3bca0b2bbffea59d0e9c00 (diff)
parent033b6c3ac3e501de569f99beac9b37f5aca73a27 (diff)
downloadtrusted-firmware-a-48b6f1783a1f2ebfe1ec66f1905e36e95bdcab15.tar.gz
Merge "drivers: stm32mp1 clocks: enable system clocks during initialization" into integration
-rw-r--r--drivers/st/clk/stm32mp1_clk.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index faf4bf6f90..4a90a7b6a7 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -2009,6 +2009,23 @@ static void stm32mp1_osc_init(void)
static void sync_earlyboot_clocks_state(void)
{
+ unsigned int idx;
+ const unsigned long secure_enable[] = {
+ AXIDCG,
+ BSEC,
+ DDRC1, DDRC1LP,
+ DDRC2, DDRC2LP,
+ DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP,
+ DDRPHYC, DDRPHYCLP,
+ TZC1, TZC2,
+ TZPC,
+ STGEN_K,
+ };
+
+ for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) {
+ stm32mp_clk_enable(secure_enable[idx]);
+ }
+
if (!stm32mp_is_single_core()) {
stm32mp1_clk_enable_secure(RTCAPB);
}