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authorSandrine Bailleux <sandrine.bailleux@arm.com>2019-12-20 10:21:59 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2019-12-20 10:21:59 +0000
commit2f227d5156c0a0a22268c3eeb1418b87345d56ac (patch)
tree00973e2f982d6be458ff3e2d8da4fb6e1dca2042
parentaeb3d83eccfe1fc18168a89cb051c6ff2b10baa0 (diff)
parent2783205da9a50b41eeb4dbd721e992457bb2151d (diff)
downloadtrusted-firmware-a-2f227d5156c0a0a22268c3eeb1418b87345d56ac.tar.gz
Merge changes from topic "tegra-boot-fixes-121719" into integration
* changes: Tegra: prepare boot parameters for Trusty Tegra: per-CPU GIC CPU interface init
-rw-r--r--plat/nvidia/tegra/common/tegra_bl31_setup.c28
-rw-r--r--plat/nvidia/tegra/common/tegra_pm.c2
2 files changed, 18 insertions, 12 deletions
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index a6652766fc..25fd84cdce 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -54,8 +54,9 @@ static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
.tzdram_size = TZDRAM_SIZE
};
-static unsigned long bl32_mem_size;
-static unsigned long bl32_boot_params;
+#ifdef SPD_trusty
+static aapcs64_params_t bl32_args;
+#endif
/*******************************************************************************
* This variable holds the non-secure image entry address
@@ -155,8 +156,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
if (arg_from_bl2->bl32_ep_info != NULL) {
bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
- bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
- bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
+#ifdef SPD_trusty
+ /* save BL32 boot parameters */
+ memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args));
+#endif
}
/*
@@ -273,17 +276,20 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
#ifdef SPD_trusty
void plat_trusty_set_boot_args(aapcs64_params_t *args)
{
- args->arg0 = bl32_mem_size;
- args->arg1 = bl32_boot_params;
- args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
+ /*
+ * arg0 = TZDRAM aperture available for BL32
+ * arg1 = BL32 boot params
+ * arg2 = EKS Blob Length
+ * arg3 = Boot Profiler Carveout Base
+ */
+ args->arg0 = bl32_args.arg0;
+ args->arg1 = bl32_args.arg2;
/* update EKS size */
- if (args->arg4 != 0U) {
- args->arg2 = args->arg4;
- }
+ args->arg2 = bl32_args.arg4;
/* Profiler Carveout Base */
- args->arg3 = args->arg5;
+ args->arg3 = bl32_args.arg5;
}
#endif
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index a8c70eaa5b..39dc42c5ba 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -244,7 +244,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
/*
* Initialize the GIC cpu and distributor interfaces
*/
- tegra_gic_init();
+ tegra_gic_pcpu_init();
/*
* Check if we are exiting from deep sleep.