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authorChandni Cherukuri <chandni.cherukuri@arm.com>2019-02-22 16:44:49 +0530
committerChandni Cherukuri <chandni.cherukuri@arm.com>2019-02-27 12:34:39 +0530
commit240f03b783bb1e531c55badf601c52c5f927f2d2 (patch)
tree3a9eb9e63357299c58c16eec0d16a3398558162b
parentf717eca9e5a169b7f4a7a68200d2b6d74baf1a17 (diff)
downloadtrusted-firmware-a-240f03b783bb1e531c55badf601c52c5f927f2d2.tar.gz
board/rde1edge: rename sgiclarkh to rde1edge
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with 'rde1edge' as per the updated product names. Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
-rw-r--r--plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts (renamed from plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts)4
-rw-r--r--plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts (renamed from plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts)0
-rw-r--r--plat/arm/board/rde1edge/include/platform_def.h (renamed from plat/arm/board/sgiclarkh/include/platform_def.h)6
-rw-r--r--plat/arm/board/rde1edge/platform.mk (renamed from plat/arm/board/sgiclarkh/platform.mk)14
-rw-r--r--plat/arm/board/rde1edge/rde1edge_plat.c (renamed from plat/arm/board/sgiclarkh/sgiclarkh_plat.c)0
-rw-r--r--plat/arm/board/rde1edge/rde1edge_security.c40
-rw-r--r--plat/arm/board/sgiclarkh/sgiclarkh_security.c40
-rw-r--r--readme.rst2
8 files changed, 53 insertions, 53 deletions
diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
index 3dedf1de2a..41769217a9 100644
--- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts
+++ b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
/dts-v1/;
/ {
/* compatible string */
- compatible = "arm,sgi-clark";
+ compatible = "arm,rd-e1edge";
/*
* Place holder for system-id node with default values. The
diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
index 766dc00f55..766dc00f55 100644
--- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts
+++ b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
diff --git a/plat/arm/board/sgiclarkh/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
index fe8907bee6..954a1cd489 100644
--- a/plat/arm/board/sgiclarkh/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,8 +18,8 @@
#define PLAT_CSS_MHU_BASE UL(0x45400000)
/* Base address of DMC-620 instances */
-#define SGICLARKH_DMC620_BASE0 UL(0x4e000000)
-#define SGICLARKH_DMC620_BASE1 UL(0x4e100000)
+#define RDE1EDGE_DMC620_BASE0 UL(0x4e000000)
+#define RDE1EDGE_DMC620_BASE1 UL(0x4e100000)
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
diff --git a/plat/arm/board/sgiclarkh/platform.mk b/plat/arm/board/rde1edge/platform.mk
index 1e93d939c2..833bb821af 100644
--- a/plat/arm/board/sgiclarkh/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -6,34 +6,34 @@
include plat/arm/css/sgi/sgi-common.mk
-SGICLARKH_BASE = plat/arm/board/sgiclarkh
+RDE1EDGE_BASE = plat/arm/board/rde1edge
-PLAT_INCLUDES += -I${SGICLARKH_BASE}/include/
+PLAT_INCLUDES += -I${RDE1EDGE_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
BL1_SOURCES += ${SGI_CPU_SOURCES}
-BL2_SOURCES += ${SGICLARKH_BASE}/sgiclarkh_plat.c \
- ${SGICLARKH_BASE}/sgiclarkh_security.c \
+BL2_SOURCES += ${RDE1EDGE_BASE}/rde1edge_plat.c \
+ ${RDE1EDGE_BASE}/rde1edge_security.c \
drivers/arm/tzc/tzc_dmc620.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
- ${SGICLARKH_BASE}/sgiclarkh_plat.c \
+ ${RDE1EDGE_BASE}/rde1edge_plat.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_tb_fw_config.dts
+FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
-FDT_SOURCES += ${SGICLARKH_BASE}/fdts/${PLAT}_nt_fw_config.dts
+FDT_SOURCES += ${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_plat.c b/plat/arm/board/rde1edge/rde1edge_plat.c
index a1b8d621d6..a1b8d621d6 100644
--- a/plat/arm/board/sgiclarkh/sgiclarkh_plat.c
+++ b/plat/arm/board/rde1edge/rde1edge_plat.c
diff --git a/plat/arm/board/rde1edge/rde1edge_security.c b/plat/arm/board/rde1edge/rde1edge_security.c
new file mode 100644
index 0000000000..2123e09311
--- /dev/null
+++ b/plat/arm/board/rde1edge/rde1edge_security.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/arm/tzc_dmc620.h>
+
+uintptr_t rde1edge_dmc_base[] = {
+ RDE1EDGE_DMC620_BASE0,
+ RDE1EDGE_DMC620_BASE1
+};
+
+static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
+ .dmc_base = rde1edge_dmc_base,
+ .dmc_count = ARRAY_SIZE(rde1edge_dmc_base)
+};
+
+static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
+ {
+ .region_base = ARM_AP_TZC_DRAM1_BASE,
+ .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
+ .sec_attr = TZC_DMC620_REGION_S_RDWR
+ }
+};
+
+static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
+ .plat_drv_data = &rde1edge_plat_driver_data,
+ .plat_acc_addr_data = rde1edge_acc_addr_data,
+ .acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data)
+};
+
+/* Initialize the secure environment */
+void plat_arm_security_setup(void)
+{
+ arm_tzc_dmc620_setup(&rde1edge_plat_config_data);
+}
diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_security.c b/plat/arm/board/sgiclarkh/sgiclarkh_security.c
deleted file mode 100644
index aaf9691ced..0000000000
--- a/plat/arm/board/sgiclarkh/sgiclarkh_security.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
-
-uintptr_t sgiclarkh_dmc_base[] = {
- SGICLARKH_DMC620_BASE0,
- SGICLARKH_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t sgiclarkh_plat_driver_data = {
- .dmc_base = sgiclarkh_dmc_base,
- .dmc_count = ARRAY_SIZE(sgiclarkh_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t sgiclarkh_acc_addr_data[] = {
- {
- .region_base = ARM_AP_TZC_DRAM1_BASE,
- .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
- .sec_attr = TZC_DMC620_REGION_S_RDWR
- }
-};
-
-static const tzc_dmc620_config_data_t sgiclarkh_plat_config_data = {
- .plat_drv_data = &sgiclarkh_plat_driver_data,
- .plat_acc_addr_data = sgiclarkh_acc_addr_data,
- .acc_addr_count = ARRAY_SIZE(sgiclarkh_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- arm_tzc_dmc620_setup(&sgiclarkh_plat_config_data);
-}
diff --git a/readme.rst b/readme.rst
index 2d7af7581e..ae9ca80313 100644
--- a/readme.rst
+++ b/readme.rst
@@ -194,7 +194,7 @@ This release also contains the following platform support:
- Allwinner sun50i_64 and sun50i_h6
- Amlogic Meson S905 (GXBB)
-- Arm SGI-575, RDN1Edge, SGI Clark.H and SGM-775
+- Arm SGI-575, RDN1Edge, RDE1Edge and SGM-775
- Arm Neoverse N1 System Development Platform
- HiKey, HiKey960 and Poplar boards
- Marvell Armada 3700 and 8K