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authorSandrine Bailleux <sandrine.bailleux@arm.com>2019-08-06 11:04:10 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2019-08-06 11:04:10 +0000
commit0d7b0963cf33c7bbabdd112e6ecf84a2f02fe676 (patch)
treede85590857a5d7e8332d0040cf6caefecaeb44ef
parent35c28cc9c9cf90b76ecb3d47637b566d37beb64c (diff)
parentb4694a8677a58546a078c38b9a841c67653b3ca9 (diff)
downloadtrusted-firmware-a-0d7b0963cf33c7bbabdd112e6ecf84a2f02fe676.tar.gz
Merge "meson: gxl: Fix CPU hotplug" into integration
-rw-r--r--plat/meson/gxl/gxl_pm.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/plat/meson/gxl/gxl_pm.c b/plat/meson/gxl/gxl_pm.c
index 5136c89aa..4a5d26e90 100644
--- a/plat/meson/gxl/gxl_pm.c
+++ b/plat/meson/gxl/gxl_pm.c
@@ -162,7 +162,8 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
*target_state)
{
- unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+ u_register_t mpidr = read_mpidr_el1();
+ unsigned int core = plat_gxbb_calc_core_pos(mpidr);
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
if (core == GXBB_PRIMARY_CPU) {
@@ -173,10 +174,19 @@ static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
VERBOSE("BL31: CPU0 resumed.\n");
- write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
+ /*
+ * Because setting CPU0's warm reset entrypoint through PSCI
+ * mailbox and/or mmio mapped RVBAR (0xda834650) does not seem
+ * to work, jump to it manually.
+ * In order to avoid an assert, mmu has to be disabled.
+ */
+ disable_mmu_el3();
+ ((void(*)(void))gxbb_sec_entrypoint)();
}
dsbsy();
+ gxl_pm_set_reset_addr(mpidr, 0);
+ gxl_pm_reset(mpidr);
for (;;)
wfi();