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author | Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> | 2020-10-09 14:51:41 +0100 |
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committer | Manish Pandey <manish.pandey2@arm.com> | 2020-10-20 20:06:48 +0000 |
commit | 2b036b79950db23e3ce9a1a8d5f2f702a1206f5c (patch) | |
tree | 84ae5f2c0ea09c05d0d60f3c06285e89a9b3685c | |
parent | 062f8aaf8a415497191f991a744fc7901362ba3c (diff) | |
download | trusted-firmware-a-2b036b79950db23e3ce9a1a8d5f2f702a1206f5c.tar.gz |
lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
Include EL2 registers related to SPE in EL2 context save/restore
routines if architecture supports it and platform wants to use these
features in Secure world.
Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-rw-r--r-- | lib/el3_runtime/aarch64/context.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index c942c10ece..773082a85e 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -94,8 +94,12 @@ func el2_sysregs_context_save stp x13, x14, [x0, #CTX_ICH_VMCR_EL2] mrs x15, mdcr_el2 +#if ENABLE_SPE_FOR_LOWER_ELS mrs x16, PMSCR_EL2 stp x15, x16, [x0, #CTX_MDCR_EL2] +#else + str x15, [x0, #CTX_MDCR_EL2] +#endif mrs x17, sctlr_el2 mrs x9, spsr_el2 @@ -291,9 +295,13 @@ func el2_sysregs_context_restore msr ICH_VMCR_EL2, x13 msr mair_el2, x14 +#if ENABLE_SPE_FOR_LOWER_ELS ldp x15, x16, [x0, #CTX_MDCR_EL2] - msr mdcr_el2, x15 msr PMSCR_EL2, x16 +#else + ldr x15, [x0, #CTX_MDCR_EL2] +#endif + msr mdcr_el2, x15 ldp x17, x9, [x0, #CTX_SCTLR_EL2] msr sctlr_el2, x17 |