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authorArunachalam Ganapathy <arunachalam.ganapathy@arm.com>2020-05-28 11:57:09 +0100
committerManish Pandey <manish.pandey2@arm.com>2020-10-20 20:06:43 +0000
commit062f8aaf8a415497191f991a744fc7901362ba3c (patch)
tree193bb7e4b55087787f6b19b7117964b0ea28a6e1
parent0f777eabd99d4bf40acf0a215112160502917172 (diff)
downloadtrusted-firmware-a-062f8aaf8a415497191f991a744fc7901362ba3c.tar.gz
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-rw-r--r--Makefile2
-rw-r--r--docs/getting_started/build-options.rst4
-rw-r--r--lib/el3_runtime/aarch64/context.S4
-rw-r--r--make_helpers/defaults.mk5
4 files changed, 15 insertions, 0 deletions
diff --git a/Makefile b/Makefile
index c5073e016b..961423826a 100644
--- a/Makefile
+++ b/Makefile
@@ -865,6 +865,7 @@ $(eval $(call assert_booleans,\
CTX_INCLUDE_PAUTH_REGS \
CTX_INCLUDE_MTE_REGS \
CTX_INCLUDE_EL2_REGS \
+ CTX_INCLUDE_NEVE_REGS \
DEBUG \
DYN_DISABLE_AUTH \
EL3_EXCEPTION_HANDLING \
@@ -953,6 +954,7 @@ $(eval $(call add_defines,\
EL3_EXCEPTION_HANDLING \
CTX_INCLUDE_MTE_REGS \
CTX_INCLUDE_EL2_REGS \
+ CTX_INCLUDE_NEVE_REGS \
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
ENABLE_AMU \
ENABLE_ASSERTIONS \
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 40fc5dbbc9..8adf4ad8ba 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -161,6 +161,10 @@ Common build options
registers to be included when saving and restoring the CPU context. Default
is 0.
+- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the
+ Armv8.4-NV registers to be saved/restored when entering/exiting an EL2
+ execution context. Default value is 0.
+
- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
registers to be included when saving and restoring the CPU context as
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 785e850934..c942c10ece 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -200,8 +200,10 @@ func el2_sysregs_context_save
mrs x12, vdisr_el2
str x12, [x0, #CTX_VDISR_EL2]
+#if CTX_INCLUDE_NEVE_REGS
mrs x13, vncr_el2
str x13, [x0, #CTX_VNCR_EL2]
+#endif
mrs x14, vsesr_el2
str x14, [x0, #CTX_VSESR_EL2]
@@ -395,8 +397,10 @@ func el2_sysregs_context_restore
ldr x13, [x0, #CTX_VDISR_EL2]
msr vdisr_el2, x13
+#if CTX_INCLUDE_NEVE_REGS
ldr x14, [x0, #CTX_VNCR_EL2]
msr vncr_el2, x14
+#endif
ldr x15, [x0, #CTX_VSESR_EL2]
msr vsesr_el2, x15
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index bc4982d64d..578bd59876 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -62,6 +62,11 @@ CTX_INCLUDE_FPREGS := 0
# world. It is not needed to use it in the Non-secure world.
CTX_INCLUDE_PAUTH_REGS := 0
+# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
+# This must be set to 1 if architecture implements Nested Virtualization
+# Extension and platform wants to use this feature in the Secure world
+CTX_INCLUDE_NEVE_REGS := 0
+
# Debug build
DEBUG := 0