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authorVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>2020-04-06 13:54:50 +0530
committerVijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>2020-04-07 18:41:13 +0530
commitb24ece54e040537599d3c94bb2b2f639bd5c2509 (patch)
tree8aae8eb4d86e581e8690d28c858d5ab4d00feb2c
parente6e10ecc42b48f3d2f49b20bb4d0cf7cc4f4c180 (diff)
downloadtrusted-firmware-a-b24ece54e040537599d3c94bb2b2f639bd5c2509.tar.gz
gic multichip: add support for clayton
GIC-Clayton supports multichip operation mode which allows it to connect upto 16 other GIC-Clayton instances. GIC-Clayton's multichip programming and operation remains same as GIC-600 with a minor change in the SPI_BLOCKS and SPI_BLOCK_MIN shifts to accommodate additional SPI ranges. So identify if the GIC v4 extension is enabled by the platform makefile and appropriately select the SPI_BLOCKS and SPI_BLOCK_MIN shifts. Change-Id: I95fd80ef16af6c7ca09e2335539187b133052d41 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
-rw-r--r--drivers/arm/gic/v3/gic600_multichip_private.h14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h
index b0217b6d41..fe4134cba9 100644
--- a/drivers/arm/gic/v3/gic600_multichip_private.h
+++ b/drivers/arm/gic/v3/gic600_multichip_private.h
@@ -24,11 +24,21 @@
/* GIC600 GICD multichip related shifts */
#define GICD_CHIPRx_ADDR_SHIFT 16
-#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10
-#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5
#define GICD_CHIPSR_RTS_SHIFT 4
#define GICD_DCHIPR_RT_OWNER_SHIFT 4
+/*
+ * If GIC v4 extension is enabled, then use SPI macros specific to GIC-Clayton.
+ * Other shifts and mask remains same between GIC-600 and GIC-Clayton.
+ */
+#if GIC_ENABLE_V4_EXTN
+#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 9
+#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 3
+#else
+#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10
+#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5
+#endif
+
#define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0)
#define GICD_CHIPSR_RTS_STATE_UPDATING U(1)
#define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2)