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author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2018-01-29 11:42:42 +0800 |
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committer | Haojian Zhuang <haojian.zhuang@linaro.org> | 2018-03-05 09:51:33 +0800 |
commit | a9b3021e145c7174f08465e88e6aba65a4099fdf (patch) | |
tree | 46fd092c9247f1519f3dab7bf29b1b8794db23d0 | |
parent | 103c213c0d82f08cf72c3e4de435bab9683d4ed5 (diff) | |
download | trusted-firmware-a-a9b3021e145c7174f08465e88e6aba65a4099fdf.tar.gz |
hikey: clean dcache for SRAM after initialized
Although SRAM is initialized, DCACHE should be cleaned too.
Because MCU is a parrallel core to access SRAM. We need to make
sure that initialized value is really written to SRAM before
MCU using it.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
-rw-r--r-- | plat/hisilicon/hikey/hikey_bl2_setup.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c index 810f6aaa02..6080f84f2f 100644 --- a/plat/hisilicon/hikey/hikey_bl2_setup.c +++ b/plat/hisilicon/hikey/hikey_bl2_setup.c @@ -276,6 +276,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) /* Clear SRAM since it'll be used by MCU right now. */ memset((void *)SRAM_BASE, 0, SRAM_SIZE); + clean_dcache_range(SRAM_BASE, SRAM_SIZE); sp804_timer_init(SP804_TIMER0_BASE, 10, 192); dsb(); |