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author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-05-15 11:43:22 +0100 |
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committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-06-04 15:37:36 +0100 |
commit | 8aa94a0ec35c6745fc62ac98ec36b9b2d0667fa5 (patch) | |
tree | 4cc750f761a1fa7e61f1ecd1cac22649d11818c5 | |
parent | 8a40778c7509c15f3251950f42e1ea7162b4ed9c (diff) | |
download | trusted-firmware-a-8aa94a0ec35c6745fc62ac98ec36b9b2d0667fa5.tar.gz |
juno: Increase L2RAM wait state to support higher cluster frequencies
Change-Id: I7f1fb4ed01ed73de1196ca17ed6fc1524478ec75
-rw-r--r-- | lib/aarch64/cpu_helpers.S | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/lib/aarch64/cpu_helpers.S b/lib/aarch64/cpu_helpers.S index abb996d69b..b8be34027c 100644 --- a/lib/aarch64/cpu_helpers.S +++ b/lib/aarch64/cpu_helpers.S @@ -43,13 +43,20 @@ func cpu_reset_handler lsr x0, x0, #MIDR_PN_SHIFT and x0, x0, #MIDR_PN_MASK cmp x0, #MIDR_PN_A57 - b.eq smp_setup_begin + b.eq a57_setup_begin cmp x0, #MIDR_PN_A53 - b.ne smp_setup_end + b.eq smp_setup_begin + b smp_setup_end + +a57_setup_begin: + mov x0, #0x082 + msr s3_1_c11_c0_2, x0 + smp_setup_begin: mrs x0, CPUECTLR_EL1 orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 isb + smp_setup_end: ret |