diff options
author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-05-22 15:28:26 +0100 |
---|---|---|
committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2014-05-23 11:05:44 +0100 |
commit | a37255a205fa004bfc075aca81cef45b99dc30cb (patch) | |
tree | b7ff04d96b7d675c22e95a1ce4734b00128292cd | |
parent | 4f59d8359f97e031c212032afeb57124ac4fcd94 (diff) | |
download | trusted-firmware-a-a37255a205fa004bfc075aca81cef45b99dc30cb.tar.gz |
Make the memory layout more flexible
Currently the platform code gets to define the base address of each
boot loader image. However, the linker scripts couteract this
flexibility by enforcing a fixed overall layout of the different
images. For example, they require that the BL3-1 image sits below
the BL2 image. Choosing BL3-1 and BL2 base addresses in such a way
that it violates this constraint makes the build fail at link-time.
This patch requires the platform code to now define a limit address
for each image. The linker scripts check that the image fits within
these bounds so they don't rely anymore on the position of a given
image in regard to the others.
Fixes ARM-software/tf-issues#163
Change-Id: I8c108646825da19a6a8dfb091b613e1dd4ae133c
-rw-r--r-- | bl1/bl1.ld.S | 8 | ||||
-rw-r--r-- | bl2/bl2.ld.S | 2 | ||||
-rw-r--r-- | bl31/bl31.ld.S | 2 | ||||
-rw-r--r-- | bl32/tsp/tsp.ld.S | 2 | ||||
-rw-r--r-- | plat/fvp/platform.h | 10 |
5 files changed, 20 insertions, 4 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 11b9a8f0a7..1af2a32deb 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -118,11 +118,17 @@ SECTIONS __DATA_ROM_START__ = LOADADDR(.data); __DATA_SIZE__ = SIZEOF(.data); + /* + * The .data section is the last PROGBITS section so its end marks the end + * of the read-only part of BL1's binary. + */ + ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= BL1_RO_LIMIT, + "BL1's RO section has exceeded its limit.") __BSS_SIZE__ = SIZEOF(.bss); __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; - ASSERT(. <= BL31_BASE, "BL1 image overlaps BL31 image.") + ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") } diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index edb676af21..9f02e92c9c 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -117,4 +117,6 @@ SECTIONS __BSS_SIZE__ = SIZEOF(.bss); __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; + + ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") } diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 1b818f5ebf..068d318162 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -126,5 +126,5 @@ SECTIONS __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; - ASSERT(. <= BL2_BASE, "BL31 image overlaps BL2 image.") + ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.") } diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index 559ae3d3bc..c72fefbdae 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -119,5 +119,5 @@ SECTIONS __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; - ASSERT(. <= BL32_LIMIT, "BL3-2 image does not fit.") + ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.") } diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h index ff87cf80bf..7fdbf81caf 100644 --- a/plat/fvp/platform.h +++ b/plat/fvp/platform.h @@ -237,21 +237,29 @@ /******************************************************************************* * BL1 specific defines. - * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of * addresses. ******************************************************************************/ #define BL1_RO_BASE TZROM_BASE +#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) #define BL1_RW_BASE TZRAM_BASE +#define BL1_RW_LIMIT BL31_BASE /******************************************************************************* * BL2 specific defines. ******************************************************************************/ #define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000) +#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* * BL31 specific defines. ******************************************************************************/ #define BL31_BASE (TZRAM_BASE + 0x6000) +#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM +#define BL31_LIMIT BL32_BASE +#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM +#define BL31_LIMIT BL2_BASE +#endif /******************************************************************************* * BL32 specific defines. |