aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorUsama Arif <usama.arif@arm.com>2020-08-26 14:04:31 +0100
committerManish Pandey <manish.pandey2@arm.com>2020-10-20 20:07:17 +0000
commit879b5b8bcaf8c03940e571628838c8476cb69dca (patch)
tree81635f350df2b41ac01329231c6da9663b04ccee
parentb0d127515a8f0694f884e4b1790cf57b0e1d91fe (diff)
downloadtrusted-firmware-a-879b5b8bcaf8c03940e571628838c8476cb69dca.tar.gz
plat: tc0: Configure TZC with secure world regions
This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-rw-r--r--plat/arm/board/tc0/include/platform_def.h11
-rw-r--r--plat/arm/board/tc0/tc0_security.c2
2 files changed, 12 insertions, 1 deletions
diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
index dbec706fac..72a035f0ab 100644
--- a/plat/arm/board/tc0/include/platform_def.h
+++ b/plat/arm/board/tc0/include/platform_def.h
@@ -249,6 +249,17 @@
#define PLAT_ARM_TZC_NS_DEV_ACCESS \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
+/*
+ * The first region below, TC0_TZC_DRAM1_BASE (0xfd000000) to
+ * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as
+ * secure. The second region gives non secure access to rest of DRAM.
+ */
+#define TC0_TZC_REGIONS_DEF \
+ {TC0_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
+ TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {TC0_NS_DRAM1_BASE, TC0_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}
+
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
diff --git a/plat/arm/board/tc0/tc0_security.c b/plat/arm/board/tc0/tc0_security.c
index 5f1cb1159b..f543762036 100644
--- a/plat/arm/board/tc0/tc0_security.c
+++ b/plat/arm/board/tc0/tc0_security.c
@@ -8,7 +8,7 @@
#include <platform_def.h>
static const arm_tzc_regions_info_t tzc_regions[] = {
- ARM_TZC_REGIONS_DEF,
+ TC0_TZC_REGIONS_DEF,
{}
};