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author | Jagadeesh Ujja <jagadeesh.ujja@arm.com> | 2020-10-07 19:51:46 +0530 |
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committer | jagadeesh.ujja <jagadeesh.ujja@arm.com> | 2020-10-09 10:43:13 +0000 |
commit | 3e0a861e3c7b7594e617a9390ab06441abb1293f (patch) | |
tree | 17ac62fe1e91e6dc2cb7f991c38c97e3df57eef2 | |
parent | 390181a4334c6d6425e2d97988b26e0ed0a93235 (diff) | |
download | trusted-firmware-a-3e0a861e3c7b7594e617a9390ab06441abb1293f.tar.gz |
lib/cpus: update MIDR value for rainier cpu
This patch updates the MIDR value for rainier cpu.
Change-Id: I99a5d96f757239cf65b2688095c4ec66cd991cf9
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
-rw-r--r-- | include/lib/cpus/aarch64/rainier.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h index 9ff1669563..978661ff69 100644 --- a/include/lib/cpus/aarch64/rainier.h +++ b/include/lib/cpus/aarch64/rainier.h @@ -10,7 +10,7 @@ #include <lib/utils_def.h> /* RAINIER MIDR for revision 0 */ -#define RAINIER_MIDR U(0x3f0f4100) +#define RAINIER_MIDR U(0x3f0f4120) /* Exception Syndrome register EC code for IC Trap */ #define RAINIER_EC_IC_TRAP U(0x1f) |