diff options
author | Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> | 2020-05-26 11:32:35 +0100 |
---|---|---|
committer | Manish Pandey <manish.pandey2@arm.com> | 2020-10-20 20:06:36 +0000 |
commit | 0f777eabd99d4bf40acf0a215112160502917172 (patch) | |
tree | 043398ef0e59b4f99b9d9c9774eae7806d021ad1 | |
parent | 32269499cc5f66564a2ea420a33e369373c2de0c (diff) | |
download | trusted-firmware-a-0f777eabd99d4bf40acf0a215112160502917172.tar.gz |
lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context
AArch64-only platforms do not implement AArch32 at EL1 and higher ELs.
In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0.
So don't save/restore aarch32 system registers in el2_sysregs_context
save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0.
Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-rw-r--r-- | lib/el3_runtime/aarch64/context.S | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 1cb527d990..785e850934 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -65,9 +65,13 @@ func el2_sysregs_context_save mrs x9, cptr_el2 stp x17, x9, [x0, #CTX_CNTVOFF_EL2] - mrs x10, dbgvcr32_el2 mrs x11, elr_el2 +#if CTX_INCLUDE_AARCH32_REGS + mrs x10, dbgvcr32_el2 stp x10, x11, [x0, #CTX_DBGVCR32_EL2] +#else + str x11, [x0, #CTX_ELR_EL2] +#endif mrs x14, esr_el2 mrs x15, far_el2 @@ -185,8 +189,10 @@ func el2_sysregs_context_save mrs x9, contextidr_el2 stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] +#if CTX_INCLUDE_AARCH32_REGS mrs x10, sder32_el2 str x10, [x0, #CTX_SDER32_EL2] +#endif mrs x11, ttbr1_el2 str x11, [x0, #CTX_TTBR1_EL2] @@ -255,8 +261,12 @@ func el2_sysregs_context_restore msr cntvoff_el2, x17 msr cptr_el2, x9 +#if CTX_INCLUDE_AARCH32_REGS ldp x10, x11, [x0, #CTX_DBGVCR32_EL2] msr dbgvcr32_el2, x10 +#else + ldr x11, [x0, #CTX_ELR_EL2] +#endif msr elr_el2, x11 ldp x14, x15, [x0, #CTX_ESR_EL2] @@ -374,8 +384,10 @@ func el2_sysregs_context_restore msr cnthv_tval_el2, x9 msr contextidr_el2, x10 +#if CTX_INCLUDE_AARCH32_REGS ldr x11, [x0, #CTX_SDER32_EL2] msr sder32_el2, x11 +#endif ldr x12, [x0, #CTX_TTBR1_EL2] msr ttbr1_el2, x12 |