diff options
author | jmarinho <jose.marinho@arm.com> | 2020-12-17 20:24:50 +0000 |
---|---|---|
committer | jmarinho <jose.marinho@arm.com> | 2021-01-29 10:48:28 +0000 |
commit | cef5b5402efd5384c27722dab1136f88e3ba8a81 (patch) | |
tree | 9bc9c3a5a872ca9698bf7632290959deacbe98e9 | |
parent | b0b1ef8b1a02835318b30044b9ad5620d9b119f6 (diff) | |
download | trusted-firmware-a-cef5b5402efd5384c27722dab1136f88e3ba8a81.tar.gz |
TMP: Add qemu.virt FWU shared page
The page is currently at PA 0xe05f000
The page is used to store:
- the trial_run state variable
- the temporary rollback counter value used during a trial run (note
that this is a platform specific design: qemu has a single rollback
counter)
Signed-off-by: jmarinho <jose.marinho@arm.com>
-rw-r--r-- | plat/qemu/common/qemu_common.c | 7 | ||||
-rw-r--r-- | plat/qemu/common/qemu_trusted_boot.c | 41 | ||||
-rw-r--r-- | plat/qemu/qemu/include/platform_def.h | 16 |
3 files changed, 60 insertions, 4 deletions
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c index b26e194039..8b4a78a12a 100644 --- a/plat/qemu/common/qemu_common.c +++ b/plat/qemu/common/qemu_common.c @@ -48,6 +48,9 @@ #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \ MT_MEMORY | MT_RO | MT_SECURE) +#define MAP_FWU_SHARED_PAGE MAP_REGION_FLAT(FWU_DATA_BASE, \ + 4096, \ + MT_DEVICE | MT_RW | MT_SECURE) /* * Table of regions for various BL stages to map using the MMU. * This doesn't include TZRAM as the 'mem_layout' argument passed to @@ -66,6 +69,7 @@ static const mmap_region_t plat_qemu_mmap[] = { MAP_DEVICE2, #endif MAP_PSCI, + MAP_FWU_SHARED_PAGE, {0} }; #endif @@ -81,6 +85,9 @@ static const mmap_region_t plat_qemu_mmap[] = { #ifdef MAP_DEVICE2 MAP_DEVICE2, #endif + + MAP_FWU_SHARED_PAGE, + MAP_PSCI, MAP_NS_DRAM0, MAP_BL32_MEM, diff --git a/plat/qemu/common/qemu_trusted_boot.c b/plat/qemu/common/qemu_trusted_boot.c index 1ef7e431b8..55a214de5b 100644 --- a/plat/qemu/common/qemu_trusted_boot.c +++ b/plat/qemu/common/qemu_trusted_boot.c @@ -5,6 +5,10 @@ */ #include <plat/common/platform.h> +#include "assert.h" + +uint32_t *qemu_trial_rot_nv = (uint32_t *)QEMU_ROT_NV_CTR_ADDR; +uint32_t *qemu_trial_flag = (uint32_t *)QEMU_TRIAL_FLAG_ADDR; extern char qemu_rotpk_hash[], qemu_rotpk_hash_end[]; @@ -20,17 +24,50 @@ int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) { - *nv_ctr = 0; + if (*qemu_trial_flag) + *nv_ctr = *qemu_trial_rot_nv; + else + *nv_ctr = *(uint32_t *)SWD_NV_COUNTER; return 0; } int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) { - return 1; + /* + * In this prototype the NV rollback counter is set in the FWU Implementation (edk2-platforms: FWUpdate.c). + * The real NV counter resides in flash at offset SWD_NV_COUNTER. + * This call sets the temporary rollback counter used during a trial run. + * The value set in QEMU_ROT_NV_CTR_ADDR is visible in the edk2-platform: FWUpdate.c. + * During the complete_trial_run handler, the value in QEMU_ROT_NV_CTR_ADDR is written to flash at offset SWD_NV_COUNTER. + */ + if(*qemu_trial_flag) { + NOTICE("qemu tbbr set trial nv_ctr %d\n", nv_ctr); + *qemu_trial_rot_nv = nv_ctr; + } + + return 0; } int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) { return get_mbedtls_heap_helper(heap_addr, heap_size); } + +void plat_decrement_trial(void) +{ + (*qemu_trial_flag)--; +} + +uint32_t plat_get_trial(void) +{ + /* + * XXX: Qemu seems to initalize the memory as 0 out of a cold boot. + * We rely on this fact for correct prototype operation. + * This is a temporary assumption, the platform port must ensure that + * the trial_run is set to zero when coming out of a cold reset. + */ + + return *qemu_trial_flag; +} + diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index 9bf016a5e2..42c1d9741e 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -102,8 +102,9 @@ #define PLAT_QEMU_HOLD_STATE_WAIT 0 #define PLAT_QEMU_HOLD_STATE_GO 1 +#define FWU_SHARED_SIZE 0x1000 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) -#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) +#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE - FWU_SHARED_SIZE) /* * BL1 specific defines. @@ -119,6 +120,15 @@ #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) /* + * FWU_DATA_BASE = SEC_SRAM_BASE + SHARED_RAM_SIZE + SEC_SRAM_SIZE - SHARED_RAM_SIZE - FWU_SHARED_SIZE + * FWU_DATA_BASE = 0xe000000 + 0x1000 + 0x60000 - 0x1000 - 0x1000 = 0xe05f000 + */ +#define FWU_DATA_BASE BL1_RW_LIMIT + +#define QEMU_ROT_NV_CTR_ADDR (FWU_DATA_BASE + 0x0) +#define QEMU_TRIAL_FLAG_ADDR (FWU_DATA_BASE + 0x4) + +/* * BL2 specific defines. * * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug @@ -170,7 +180,7 @@ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#define MAX_MMAP_REGIONS 11 +#define MAX_MMAP_REGIONS 12 #define MAX_XLAT_TABLES 6 #define MAX_IO_DEVICES 4 #define MAX_IO_HANDLES 4 @@ -200,6 +210,8 @@ #define PLAT_QEMU_FIP_BASE_B 0x00280000 #define PLAT_QEMU_IMAGE_METADATA 0x00600000 +#define SWD_NV_COUNTER 0x540000 + #define PLAT_QEMU_FIP_MAX_SIZE 0x00400000 #define DEVICE0_BASE 0x08000000 |