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authorAndre Przywara <andre.przywara@arm.com>2020-01-24 15:02:27 +0000
committerAndre Przywara <andre.przywara@arm.com>2020-05-05 15:36:51 +0100
commit670c66af0667e13857405ade5af7d3c4d248abe5 (patch)
tree23a23d202592b5df2e5d8afcc31e51c9ee09447a
parent93bb7a0ac35bb1490bac0b0b667f5845f9dbdd3c (diff)
downloadtrusted-firmware-a-670c66af0667e13857405ade5af7d3c4d248abe5.tar.gz
arm_fpga: Read generic timer counter frequency from DT
The ARM Generic Timer DT binding describes an (optional) property to declare the counter frequency. Its usage is normally discouraged, as the value should be read from the CNTFRQ_EL0 system register. However in our case we can use it to program this register in the first place, which avoids us to hard code a counter frequency into the code. We keep some default value in, if the DT lacks that property for whatever reason. Change-Id: I5b71176db413f904f21eb16f3302fbb799cb0305 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-rw-r--r--plat/arm/board/arm_fpga/fpga_bl31_setup.c16
-rw-r--r--plat/arm/board/arm_fpga/fpga_def.h2
-rw-r--r--plat/arm/board/arm_fpga/platform.mk5
3 files changed, 19 insertions, 4 deletions
diff --git a/plat/arm/board/arm_fpga/fpga_bl31_setup.c b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
index 632949723b..e4b9767d40 100644
--- a/plat/arm/board/arm_fpga/fpga_bl31_setup.c
+++ b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
@@ -5,8 +5,11 @@
*/
#include <assert.h>
-#include <lib/mmio.h>
+
+#include <common/fdt_wrappers.h>
#include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <libfdt.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -76,7 +79,16 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
unsigned int plat_get_syscnt_freq2(void)
{
- return FPGA_TIMER_FREQUENCY;
+ const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
+ int node;
+
+ node = fdt_node_offset_by_compatible(fdt, 0, "arm,armv8-timer");
+ if (node < 0) {
+ return FPGA_DEFAULT_TIMER_FREQUENCY;
+ }
+
+ return fdt_read_uint32_default(fdt, node, "clock-frequency",
+ FPGA_DEFAULT_TIMER_FREQUENCY);
}
void bl31_plat_enable_mmu(uint32_t flags)
diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
index 609263745a..0bb2b22e00 100644
--- a/plat/arm/board/arm_fpga/fpga_def.h
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -31,6 +31,6 @@
#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
-#define FPGA_TIMER_FREQUENCY 10000000
+#define FPGA_DEFAULT_TIMER_FREQUENCY 10000000
#endif
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 335000037f..0d0d010a14 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -4,6 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+include lib/libfdt/libfdt.mk
+
RESET_TO_BL31 := 1
ifeq (${RESET_TO_BL31}, 0)
$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
@@ -82,7 +84,8 @@ PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
-BL31_SOURCES += drivers/delay_timer/delay_timer.c \
+BL31_SOURCES += common/fdt_wrappers.c \
+ drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/arm/pl011/${ARCH}/pl011_console.S \
plat/common/plat_psci_common.c \