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author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2020-04-09 15:03:20 +0000 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-04-09 15:03:20 +0000 |
commit | 1a63443c08f5ee2a3cd1015741c76875bf705964 (patch) | |
tree | a2883d75407fa458e0225bc4f5f6918994d24c58 | |
parent | 50d8cf26dc57bb453b1a52be646140bfea4aa591 (diff) | |
parent | a82ea1dbbf0d651d9fed35bf3a962cd8fce4b01c (diff) | |
download | trusted-firmware-a-1a63443c08f5ee2a3cd1015741c76875bf705964.tar.gz |
Merge "arm_fpga: Remove bogus timer initialisation" into integration
-rw-r--r-- | plat/arm/board/arm_fpga/fpga_bl31_setup.c | 1 | ||||
-rw-r--r-- | plat/arm/board/arm_fpga/fpga_def.h | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/plat/arm/board/arm_fpga/fpga_bl31_setup.c b/plat/arm/board/arm_fpga/fpga_bl31_setup.c index d499379ee8..632949723b 100644 --- a/plat/arm/board/arm_fpga/fpga_bl31_setup.c +++ b/plat/arm/board/arm_fpga/fpga_bl31_setup.c @@ -56,7 +56,6 @@ void bl31_platform_setup(void) /* Write frequency to CNTCRL and initialize timer */ generic_delay_timer_init(); - mmio_write_32(FPGA_TIMER_BASE, ((1 << 8) | 1UL)); } entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h index 56ee1663d3..dbdbe6f4d8 100644 --- a/plat/arm/board/arm_fpga/fpga_def.h +++ b/plat/arm/board/arm_fpga/fpga_def.h @@ -36,6 +36,5 @@ #define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ #define FPGA_TIMER_FREQUENCY 10000000 -#define FPGA_TIMER_BASE 0x2a830000 #endif |