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author | Manish Pandey <manish.pandey2@arm.com> | 2022-11-14 15:54:27 +0100 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2022-11-14 15:54:27 +0100 |
commit | e1d24114a6ca11d4896986202c2467fca5a4e62a (patch) | |
tree | 43b1a8c4b6a0d58753661222c5938da34c833c14 | |
parent | 5fab71a7dc617686b63ef5f25e03447df4f2993c (diff) | |
parent | 92f8be8fd1e77be67e9c9711afa8705204758304 (diff) | |
download | trusted-firmware-a-e1d24114a6ca11d4896986202c2467fca5a4e62a.tar.gz |
Merge changes I256959d7,I721376bf into integration
* changes:
fix(cpus): remove plat_can_cmo check for aarch32
fix(cpus): update doc and check for plat_can_cmo
-rw-r--r-- | docs/getting_started/porting-guide.rst | 4 | ||||
-rw-r--r-- | lib/aarch32/cache_helpers.S | 22 | ||||
-rw-r--r-- | lib/aarch64/cache_helpers.S | 1 |
3 files changed, 3 insertions, 24 deletions
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index 7f38054940..aa57e1db6b 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -1502,8 +1502,8 @@ When CONDITIONAL_CMO flag is enabled: - This function indicates whether cache management operations should be performed. It returns 0 if CMOs should be skipped and non-zero otherwise. -- The function must not clobber x2 and x3. It's also not safe to rely on stack. - Otherwise obey AAPCS. +- The function must not clobber x1, x2 and x3. It's also not safe to rely on + stack. Otherwise obey AAPCS. Modifications specific to a Boot Loader stage --------------------------------------------- diff --git a/lib/aarch32/cache_helpers.S b/lib/aarch32/cache_helpers.S index fd9b33f2d5..13d1872f84 100644 --- a/lib/aarch32/cache_helpers.S +++ b/lib/aarch32/cache_helpers.S @@ -37,27 +37,12 @@ exit_loop_\op: bx lr .endm -.macro check_plat_can_cmo -#if CONDITIONAL_CMO - mov r3, lr - mov r2, r0 - bl plat_can_cmo - mov lr, r3 - cmp r0, #0 - bne 1f - bx lr -1: - mov r0, r2 -#endif -.endm - /* ------------------------------------------ * Clean+Invalidate from base address till * size. 'r0' = addr, 'r1' = size * ------------------------------------------ */ func flush_dcache_range - check_plat_can_cmo do_dcache_maintenance_by_mva cimvac, DCCIMVAC endfunc flush_dcache_range @@ -67,7 +52,6 @@ endfunc flush_dcache_range * ------------------------------------------ */ func clean_dcache_range - check_plat_can_cmo do_dcache_maintenance_by_mva cmvac, DCCMVAC endfunc clean_dcache_range @@ -77,7 +61,6 @@ endfunc clean_dcache_range * ------------------------------------------ */ func inv_dcache_range - check_plat_can_cmo do_dcache_maintenance_by_mva imvac, DCIMVAC endfunc inv_dcache_range @@ -185,7 +168,6 @@ endfunc do_dcsw_op * --------------------------------------------------------------- */ func dcsw_op_louis - check_plat_can_cmo dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT endfunc dcsw_op_louis @@ -198,7 +180,6 @@ endfunc dcsw_op_louis * --------------------------------------------------------------- */ func dcsw_op_all - check_plat_can_cmo dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT endfunc dcsw_op_all @@ -224,7 +205,6 @@ endfunc dcsw_op_all * --------------------------------------------------------------- */ func dcsw_op_level1 - check_plat_can_cmo dcsw_op_level #(1 << LEVEL_SHIFT) endfunc dcsw_op_level1 @@ -237,7 +217,6 @@ endfunc dcsw_op_level1 * --------------------------------------------------------------- */ func dcsw_op_level2 - check_plat_can_cmo dcsw_op_level #(2 << LEVEL_SHIFT) endfunc dcsw_op_level2 @@ -250,6 +229,5 @@ endfunc dcsw_op_level2 * --------------------------------------------------------------- */ func dcsw_op_level3 - check_plat_can_cmo dcsw_op_level #(3 << LEVEL_SHIFT) endfunc dcsw_op_level3 diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S index 67fafb1e7a..314ed6efd7 100644 --- a/lib/aarch64/cache_helpers.S +++ b/lib/aarch64/cache_helpers.S @@ -217,6 +217,7 @@ dcsw_loop_table: func dcsw_op_louis + check_plat_can_cmo dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT endfunc dcsw_op_louis |