diff options
author | Anthony Zhou <anzhou@nvidia.com> | 2017-09-20 17:44:43 +0800 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-11-28 11:14:21 -0800 |
commit | b6533b56db2b1f3f96367604fd9b1e296f62b750 (patch) | |
tree | 0f9cbbb398b092dced7b8a2add13bcbb9ca68a5a | |
parent | 6152de3b347203e062d974b1af9b286b1f5c138c (diff) | |
download | trusted-firmware-a-b6533b56db2b1f3f96367604fd9b1e296f62b750.tar.gz |
Tegra194: fix defects flagged by MISRA scan
Main fixes:
Fix invalid use of function pointer [Rule 1.3]
Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
convert object type to match the type of function parameters
[Rule 10.3]
Force operands of an operator to the same type category [Rule 10.4]
Fix implicit widening of composite assignment [Rule 10.6]
Fixed if statement conditional to be essentially boolean [Rule 14.4]
Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
Voided non c-library functions whose return types are not used
[Rule 17.7]
Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
-rw-r--r-- | plat/nvidia/tegra/include/t194/tegra_def.h | 200 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_memctrl.c | 6 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_psci_handlers.c | 150 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_secondary.c | 12 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_setup.c | 109 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_sip_calls.c | 38 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_smmu.c | 4 |
7 files changed, 277 insertions, 242 deletions
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 66c418d3c7..2b578d5cf2 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -14,9 +14,9 @@ * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * parameter. ******************************************************************************/ -#define PSTATE_ID_CORE_IDLE 6 -#define PSTATE_ID_CORE_POWERDN 7 -#define PSTATE_ID_SOC_POWERDN 2 +#define PSTATE_ID_CORE_IDLE U(6) +#define PSTATE_ID_CORE_POWERDN U(7) +#define PSTATE_ID_SOC_POWERDN U(2) /******************************************************************************* * Platform power states (used by PSCI framework) @@ -24,192 +24,192 @@ * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID ******************************************************************************/ -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 8 +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(8) /******************************************************************************* * Secure IRQ definitions ******************************************************************************/ -#define TEGRA186_MAX_SEC_IRQS 5 -#define TEGRA186_BPMP_WDT_IRQ 46 -#define TEGRA186_SPE_WDT_IRQ 47 -#define TEGRA186_SCE_WDT_IRQ 48 -#define TEGRA186_TOP_WDT_IRQ 49 -#define TEGRA186_AON_WDT_IRQ 50 +#define TEGRA186_MAX_SEC_IRQS U(5) +#define TEGRA186_BPMP_WDT_IRQ U(46) +#define TEGRA186_SPE_WDT_IRQ U(47) +#define TEGRA186_SCE_WDT_IRQ U(48) +#define TEGRA186_TOP_WDT_IRQ U(49) +#define TEGRA186_AON_WDT_IRQ U(50) -#define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ +#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */ /******************************************************************************* * Tegra Miscellanous register constants ******************************************************************************/ -#define TEGRA_MISC_BASE 0x00100000U +#define TEGRA_MISC_BASE U(0x00100000) -#define HARDWARE_REVISION_OFFSET 0x4U -#define MISCREG_EMU_REVID 0x3160U -#define BOARD_MASK_BITS 0xFFU -#define BOARD_SHIFT_BITS 24U -#define MISCREG_PFCFG 0x200CU +#define HARDWARE_REVISION_OFFSET U(0x4) +#define MISCREG_EMU_REVID U(0x3160) +#define BOARD_MASK_BITS U(0xFF) +#define BOARD_SHIFT_BITS U(24) +#define MISCREG_PFCFG U(0x200C) /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ -#define TEGRA_MC_STREAMID_BASE 0x02C00000 -#define TEGRA_MC_BASE 0x02C10000 +#define TEGRA_MC_STREAMID_BASE U(0x02C00000) +#define TEGRA_MC_BASE U(0x02C10000) /* General Security Carveout register macros */ -#define MC_GSC_CONFIG_REGS_SIZE 0x40 -#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) -#define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) -#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 -#define MC_GSC_BASE_LO_SHIFT 12 -#define MC_GSC_BASE_LO_MASK 0xFFFFF -#define MC_GSC_BASE_HI_SHIFT 0 -#define MC_GSC_BASE_HI_MASK 3 +#define MC_GSC_CONFIG_REGS_SIZE U(0x40) +#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) +#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) +#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) +#define MC_GSC_BASE_LO_SHIFT U(12) +#define MC_GSC_BASE_LO_MASK U(0xFFFFF) +#define MC_GSC_BASE_HI_SHIFT U(0) +#define MC_GSC_BASE_HI_MASK U(3) #define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31) /* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 -#define MC_SECURITY_CFG3_0 0x9BC +#define MC_SECURITY_CFG0_0 U(0x70) +#define MC_SECURITY_CFG1_0 U(0x74) +#define MC_SECURITY_CFG3_0 U(0x9BC) #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) /* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE_HI 0x978 -#define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c +#define MC_VIDEO_PROTECT_BASE_HI U(0x978) +#define MC_VIDEO_PROTECT_BASE_LO U(0x648) +#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) /* * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the * non-overlapping Video memory region */ -#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 -#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 -#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 -#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC -#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 +#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) +#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) +#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) +#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) +#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ -#define MC_TZRAM_CARVEOUT_CFG 0x2190 -#define MC_TZRAM_BASE_LO 0x2194 -#define MC_TZRAM_BASE_HI 0x2198 -#define MC_TZRAM_SIZE 0x219C +#define MC_TZRAM_CARVEOUT_CFG U(0x2190) +#define MC_TZRAM_BASE_LO U(0x2194) +#define MC_TZRAM_BASE_HI U(0x2198) +#define MC_TZRAM_SIZE U(0x219C) #define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0) #define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4) #define TZRAM_ALLOW_MPCORER (U(1) << 7) #define TZRAM_ALLOW_MPCOREW (U(1) << 25) /* Memory Controller Reset Control registers */ -#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) -#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) -#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) -#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) +#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28) +#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29) +#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30) +#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31) /******************************************************************************* * Tegra UART Controller constants ******************************************************************************/ -#define TEGRA_UARTA_BASE 0x03100000 -#define TEGRA_UARTB_BASE 0x03110000 -#define TEGRA_UARTC_BASE 0x0C280000 -#define TEGRA_UARTD_BASE 0x03130000 -#define TEGRA_UARTE_BASE 0x03140000 -#define TEGRA_UARTF_BASE 0x03150000 -#define TEGRA_UARTG_BASE 0x0C290000 +#define TEGRA_UARTA_BASE U(0x03100000) +#define TEGRA_UARTB_BASE U(0x03110000) +#define TEGRA_UARTC_BASE U(0x0C280000) +#define TEGRA_UARTD_BASE U(0x03130000) +#define TEGRA_UARTE_BASE U(0x03140000) +#define TEGRA_UARTF_BASE U(0x03150000) +#define TEGRA_UARTG_BASE U(0x0C290000) /******************************************************************************* * Tegra Fuse Controller related constants ******************************************************************************/ -#define TEGRA_FUSE_BASE 0x03820000 -#define OPT_SUBREVISION 0x248 -#define SUBREVISION_MASK 0xF +#define TEGRA_FUSE_BASE U(0x03820000) +#define OPT_SUBREVISION U(0x248) +#define SUBREVISION_MASK U(0xF) /******************************************************************************* * GICv2 & interrupt handling related constants ******************************************************************************/ -#define TEGRA_GICD_BASE 0x03881000 -#define TEGRA_GICC_BASE 0x03882000 +#define TEGRA_GICD_BASE U(0x03881000) +#define TEGRA_GICC_BASE U(0x03882000) /******************************************************************************* * Security Engine related constants ******************************************************************************/ -#define TEGRA_SE0_BASE 0x03AC0000 -#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C -#define TEGRA_PKA1_BASE 0x03AD0000 -#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 -#define TEGRA_RNG1_BASE 0x03AE0000 -#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 +#define TEGRA_SE0_BASE U(0x03AC0000) +#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) +#define TEGRA_PKA1_BASE U(0x03AD0000) +#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) +#define TEGRA_RNG1_BASE U(0x03AE0000) +#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) /******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ -#define TEGRA_TMRUS_BASE 0x0C2E0000 -#define TEGRA_TMRUS_SIZE 0x10000 +#define TEGRA_TMRUS_BASE U(0x0C2E0000) +#define TEGRA_TMRUS_SIZE U(0x10000) /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ -#define TEGRA_PMC_BASE 0x0C360000 +#define TEGRA_PMC_BASE U(0x0C360000) /******************************************************************************* * Tegra scratch registers constants ******************************************************************************/ -#define TEGRA_SCRATCH_BASE 0x0C390000 -#define SECURE_SCRATCH_RSV1_LO 0x06C -#define SECURE_SCRATCH_RSV1_HI 0x070 -#define SECURE_SCRATCH_RSV6 0x094 -#define SECURE_SCRATCH_RSV11_LO 0x0BC -#define SECURE_SCRATCH_RSV11_HI 0x0C0 -#define SECURE_SCRATCH_RSV53_LO 0x20C -#define SECURE_SCRATCH_RSV53_HI 0x210 -#define SECURE_SCRATCH_RSV54_HI 0x218 -#define SECURE_SCRATCH_RSV55_LO 0x21C -#define SECURE_SCRATCH_RSV55_HI 0x220 +#define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV1_LO U(0x06C) +#define SECURE_SCRATCH_RSV1_HI U(0x070) +#define SECURE_SCRATCH_RSV6 U(0x094) +#define SECURE_SCRATCH_RSV11_LO U(0x0BC) +#define SECURE_SCRATCH_RSV11_HI U(0x0C0) +#define SECURE_SCRATCH_RSV53_LO U(0x20C) +#define SECURE_SCRATCH_RSV53_HI U(0x210) +#define SECURE_SCRATCH_RSV54_HI U(0x218) +#define SECURE_SCRATCH_RSV55_LO U(0x21C) +#define SECURE_SCRATCH_RSV55_HI U(0x220) /******************************************************************************* * Tegra Memory Mapped Control Register Access Bus constants ******************************************************************************/ -#define TEGRA_MMCRAB_BASE 0x0E000000 +#define TEGRA_MMCRAB_BASE U(0x0E000000) /******************************************************************************* * Tegra SMMU Controller constants ******************************************************************************/ -#define TEGRA_SMMU0_BASE 0x12000000 -#define TEGRA_SMMU1_BASE 0x11000000 -#define TEGRA_SMMU2_BASE 0x10000000 +#define TEGRA_SMMU0_BASE U(0x12000000) +#define TEGRA_SMMU1_BASE U(0x11000000) +#define TEGRA_SMMU2_BASE U(0x10000000) /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ -#define TEGRA_TZRAM_BASE 0x40000000 -#define TEGRA_TZRAM_SIZE 0x40000 +#define TEGRA_TZRAM_BASE U(0x40000000) +#define TEGRA_TZRAM_SIZE U(0x40000) /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ -#define TEGRA_CAR_RESET_BASE 0x20000000 +#define TEGRA_CAR_RESET_BASE U(0x20000000) /******************************************************************************* * XUSB PADCTL ******************************************************************************/ -#define TEGRA_XUSB_PADCTL_BASE (0x3520000U) -#define TEGRA_XUSB_PADCTL_SIZE (0x10000U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) -#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) -#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) +#define TEGRA_XUSB_PADCTL_BASE U(0x3520000) +#define TEGRA_XUSB_PADCTL_SIZE U(0x10000) +#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378) +#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c) +#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c) /******************************************************************************* * XUSB STREAMIDs ******************************************************************************/ -#define TEGRA_SID_XUSB_HOST (0x1bU) -#define TEGRA_SID_XUSB_DEV (0x1cU) -#define TEGRA_SID_XUSB_VF0 (0x5dU) -#define TEGRA_SID_XUSB_VF1 (0x5eU) -#define TEGRA_SID_XUSB_VF2 (0x5fU) -#define TEGRA_SID_XUSB_VF3 (0x60U) +#define TEGRA_SID_XUSB_HOST U(0x1b) +#define TEGRA_SID_XUSB_DEV U(0x1c) +#define TEGRA_SID_XUSB_VF0 U(0x5d) +#define TEGRA_SID_XUSB_VF1 U(0x5e) +#define TEGRA_SID_XUSB_VF2 U(0x5f) +#define TEGRA_SID_XUSB_VF3 U(0x60) #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index a9341b16b9..0bacc86c02 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -625,11 +625,11 @@ static void tegra194_memctrl_reconfig_mss_clients(void) ******************************************************************************/ static tegra_mc_settings_t tegra194_mc_settings = { .streamid_override_cfg = tegra194_streamid_override_regs, - .num_streamid_override_cfgs = ARRAY_SIZE(tegra194_streamid_override_regs), + .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs), .streamid_security_cfg = tegra194_streamid_sec_cfgs, - .num_streamid_security_cfgs = ARRAY_SIZE(tegra194_streamid_sec_cfgs), + .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs), .txn_override_cfg = tegra194_txn_override_cfgs, - .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs), + .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs), .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients }; diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c index d77842984d..9e24f41498 100644 --- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c @@ -21,8 +21,6 @@ #include <t194_nvg.h> #include <stdbool.h> -extern void prepare_core_pwr_dwn(void); - extern void tegra_secure_entrypoint(void); #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM @@ -31,23 +29,23 @@ extern uint32_t __tegra186_cpu_reset_handler_data, __tegra186_cpu_reset_handler_end; /* TZDRAM offset for saving SMMU context */ -#define TEGRA186_SMMU_CTX_OFFSET 16 +#define TEGRA186_SMMU_CTX_OFFSET 16U #endif /* state id mask */ -#define TEGRA186_STATE_ID_MASK 0xF +#define TEGRA186_STATE_ID_MASK 0xFU /* constants to get power state's wake time */ -#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0 -#define TEGRA186_WAKE_TIME_SHIFT 4 +#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0U +#define TEGRA186_WAKE_TIME_SHIFT 4U /* default core wake mask for CPU_SUSPEND */ -#define TEGRA194_CORE_WAKE_MASK 0x180c +#define TEGRA194_CORE_WAKE_MASK 0x180cU /* context size to save during system suspend */ -#define TEGRA186_SE_CONTEXT_SIZE 3 +#define TEGRA186_SE_CONTEXT_SIZE 3U static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE]; -static struct t18x_psci_percpu_data { - unsigned int wake_time; -} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT]; +static struct t19x_psci_percpu_data { + uint32_t wake_time; +} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; /* * tegra_fake_system_suspend acts as a boolean var controlling whether @@ -57,14 +55,16 @@ static struct t18x_psci_percpu_data { */ bool tegra_fake_system_suspend; -int32_t tegra_soc_validate_power_state(unsigned int power_state, +int32_t tegra_soc_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) { - int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK; - int cpu = plat_my_core_pos(); + uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & + TEGRA186_STATE_ID_MASK; + uint32_t cpu = plat_my_core_pos(); + int32_t ret = PSCI_E_SUCCESS; /* save the core wake time (in TSC ticks)*/ - percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) + t19x_percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK) << TEGRA186_WAKE_TIME_SHIFT; /* @@ -74,8 +74,8 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, * from DRAM in that function, because the L2 cache is not flushed * unless the cluster is entering CC6/CC7. */ - clean_dcache_range((uint64_t)&percpu_data[cpu], - sizeof(percpu_data[cpu])); + clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], + sizeof(t19x_percpu_data[cpu])); /* Sanity check the requested state id */ switch (state_id) { @@ -90,28 +90,29 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, default: ERROR("%s: unsupported state id (%d)\n", __func__, state_id); - return PSCI_E_INVALID_PARAMS; + ret = PSCI_E_INVALID_PARAMS; + break; } - return PSCI_E_SUCCESS; + return ret; } -int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state; - unsigned int stateid_afflvl0, stateid_afflvl2; + uint8_t stateid_afflvl0, stateid_afflvl2; #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); uint64_t smmu_ctx_base; #endif uint32_t val; mce_cstate_info_t sc7_cstate_info = { - .cluster = TEGRA_NVG_CLUSTER_CC6, - .system = TEGRA_NVG_SYSTEM_SC7, - .system_state_force = 1, - .update_wake_mask = 1, + .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, + .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, + .system_state_force = 1U, + .update_wake_mask = 1U, }; - int cpu = plat_my_core_pos(); + uint32_t cpu = plat_my_core_pos(); int32_t ret = 0; /* get the state ID */ @@ -126,8 +127,8 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* Enter CPU idle/powerdown */ val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? - TEGRA_NVG_CORE_C6 : TEGRA_NVG_CORE_C7; - ret = mce_command_handler(MCE_CMD_ENTER_CSTATE, val, + (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; + ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, percpu_data[cpu].wake_time, 0); assert(ret == 0); @@ -149,7 +150,7 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* save SMMU context */ smmu_ctx_base = params_from_bl2->tzdram_base + ((uintptr_t)&__tegra186_cpu_reset_handler_data - - (uintptr_t)tegra186_cpu_reset_handler) + + (uintptr_t)&tegra186_cpu_reset_handler) + TEGRA186_SMMU_CTX_OFFSET; tegra_smmu_save_context((uintptr_t)smmu_ctx_base); #else @@ -162,17 +163,23 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) mce_update_cstate_info(&sc7_cstate_info); do { - val = mce_command_handler( - MCE_CMD_IS_SC7_ALLOWED, - TEGRA_NVG_CORE_C7, + val = (uint32_t)mce_command_handler( + (uint32_t)MCE_CMD_IS_SC7_ALLOWED, + (uint32_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, - 0); - } while (val == 0); - - /* Instruct the MCE to enter system suspend state */ - (void)mce_command_handler(MCE_CMD_ENTER_CSTATE, - TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + 0U); + } while (val == 0U); + + /* Instruct the MCE to enter system suspend state */ + ret = mce_command_handler( + (uint64_t)MCE_CMD_ENTER_CSTATE, + (uint64_t)TEGRA_NVG_CORE_C7, + MCE_CORE_SLEEP_TIME_INFINITE, + 0U); + assert(ret == 0); } + } else { + ; /* do nothing */ } return PSCI_E_SUCCESS; @@ -182,20 +189,21 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) * Platform handler to calculate the proper target power level at the * specified affinity level ******************************************************************************/ -plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, +plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, const plat_local_state_t *states, - unsigned int ncpu) + uint32_t ncpu) { plat_local_state_t target = *states; - int cluster_powerdn = 1; - int core_pos = read_mpidr() & MPIDR_CPU_MASK; + int32_t cluster_powerdn = 1; + uint32_t core_pos = (uint32_t)read_mpidr() & MPIDR_CPU_MASK; + uint32_t num_cpus = ncpu, pos = 0; mce_cstate_info_t cstate_info = { 0 }; /* get the current core's power state */ - target = *(states + core_pos); + target = states[core_pos]; /* CPU suspend */ - if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) { + if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CORE_POWERDN)) { /* Program default wake mask */ cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; @@ -204,17 +212,20 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, } /* CPU off */ - if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) { + if ((lvl == MPIDR_AFFLVL1) && (target == PLAT_MAX_OFF_STATE)) { /* find out the number of ON cpus in the cluster */ do { - target = *states++; - if (target != PLAT_MAX_OFF_STATE) + target = states[pos]; + if (target != PLAT_MAX_OFF_STATE) { cluster_powerdn = 0; - } while (--ncpu); + } + --num_cpus; + pos++; + } while (num_cpus != 0U); /* Enable cluster powerdn from last CPU in the cluster */ - if (cluster_powerdn) { + if (cluster_powerdn != 0) { /* Enable CC6 */ /* todo */ @@ -234,20 +245,21 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, } /* System Suspend */ - if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) + if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN)) { return PSTATE_ID_SOC_POWERDN; + } /* default state */ return PSCI_LOCAL_STATE_RUN; } #if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM -int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) { const plat_local_state_t *pwr_domain_state = target_state->pwr_domain_state; plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); - unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & + uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & TEGRA186_STATE_ID_MASK; uint64_t val; u_register_t ns_sctlr_el1; @@ -264,7 +276,6 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); - /* * In fake suspend mode, ensure that the loopback procedure * towards system suspend exit is started, instead of calling @@ -294,11 +305,12 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) } #endif -int tegra_soc_pwr_domain_on(u_register_t mpidr) +int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) { - uint32_t target_cpu = mpidr & MPIDR_CPU_MASK; - uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> + uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; + uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + int32_t ret = 0; if (target_cluster > MPIDR_AFFLVL1) { ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); @@ -306,16 +318,19 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr) } /* construct the target CPU # */ - target_cpu += (target_cluster << 1); + target_cpu += (target_cluster << 1U); - mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0); + ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); + if (ret < 0) { + return PSCI_E_DENIED; + } return PSCI_E_SUCCESS; } -int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) { - int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; + uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; /* * Reset power state info for CPUs when onlining, we set @@ -353,18 +368,21 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } -int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) +int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) { - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; int32_t ret = 0; + (void)target_state; + /* Disable Denver's DCO operations */ - if (impl == DENVER_IMPL) + if (impl == DENVER_IMPL) { denver_disable_dco(); + } /* Turn off CPU */ - ret = mce_command_handler(MCE_CMD_ENTER_CSTATE, - TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0); + ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, + (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); assert(ret == 0); return PSCI_E_SUCCESS; @@ -384,7 +402,7 @@ __dead2 void tegra_soc_prepare_system_off(void) } } -int tegra_soc_prepare_system_reset(void) +int32_t tegra_soc_prepare_system_reset(void) { return PSCI_E_SUCCESS; } diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c index f5e56b9b07..c54ca28b8d 100644 --- a/plat/nvidia/tegra/soc/t194/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c @@ -12,11 +12,11 @@ #include <tegra_def.h> #include <tegra_private.h> -#define MISCREG_CPU_RESET_VECTOR 0x2000 -#define MISCREG_AA64_RST_LOW 0x2004 -#define MISCREG_AA64_RST_HIGH 0x2008 +#define MISCREG_CPU_RESET_VECTOR 0x2000U +#define MISCREG_AA64_RST_LOW 0x2004U +#define MISCREG_AA64_RST_HIGH 0x2008U -#define CPU_RESET_MODE_AA64 1 +#define CPU_RESET_MODE_AA64 1U extern void tegra_secure_entrypoint(void); @@ -44,11 +44,11 @@ void plat_secondary_setup(void) memcpy((void *)((uintptr_t)cpu_reset_handler_base), (void *)(uintptr_t)tegra186_cpu_reset_handler, (uintptr_t)&__tegra186_smmu_ctx_start - - (uintptr_t)tegra186_cpu_reset_handler); + (uintptr_t)&tegra186_cpu_reset_handler); #endif addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; - addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); + addr_high = (uint32_t)((cpu_reset_handler_base >> 32U) & 0x7ffU); /* write lower 32 bits first, then the upper 11 bits */ mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index b325e4e0dd..08bd71073c 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -32,7 +32,7 @@ * the number of power domains at the highest power level. ******************************************************************************* */ -const unsigned char tegra_power_domain_tree_desc[] = { +static const uint8_t tegra_power_domain_tree_desc[] = { /* No of root nodes */ 1, /* No of clusters */ @@ -50,7 +50,7 @@ const unsigned char tegra_power_domain_tree_desc[] = { /******************************************************************************* * This function returns the Tegra default topology tree information. ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) +const uint8_t *plat_get_power_domain_tree_desc(void) { return tegra_power_domain_tree_desc; } @@ -59,46 +59,46 @@ const unsigned char *plat_get_power_domain_tree_desc(void) * Table of regions to map using the MMU. */ static const mmap_region_t tegra_mmap[] = { - MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), - MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000, /* 64KB */ - MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), + MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */ + (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE), {0} }; @@ -114,7 +114,7 @@ const mmap_region_t *plat_get_mmio_map(void) /******************************************************************************* * Handler to get the System Counter Frequency ******************************************************************************/ -unsigned int plat_get_syscnt_freq2(void) +uint32_t plat_get_syscnt_freq2(void) { return 31250000; } @@ -135,18 +135,23 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { TEGRA_UARTD_BASE, TEGRA_UARTE_BASE, TEGRA_UARTF_BASE, - TEGRA_UARTG_BASE, + TEGRA_UARTG_BASE }; /******************************************************************************* * Retrieve the UART controller base to be used as the console ******************************************************************************/ -uint32_t plat_get_console_from_id(int id) +uint32_t plat_get_console_from_id(int32_t id) { - if (id > TEGRA186_MAX_UART_PORTS) - return 0; + uint32_t ret; - return tegra186_uart_addresses[id]; + if (id > TEGRA186_MAX_UART_PORTS) { + ret = 0; + } else { + ret = tegra186_uart_addresses[id]; + } + + return ret; } /******************************************************************************* @@ -189,7 +194,7 @@ void plat_early_platform_setup(void) * Known Limitations: * If xusb interface disables SMMU in XUSB DT in non-virtualization * setup then there will be SMMU fault. We need to use WAR at - * https://git-master.nvidia.com/r/1529227/ to the issue. + * https:\\git-master.nvidia.com/r/1529227/ to the issue. * * More details can be found in the bug 1971161 */ @@ -246,15 +251,15 @@ static const irq_sec_cfg_t tegra186_sec_irqs[] = { ******************************************************************************/ void plat_gic_setup(void) { - tegra_gic_setup(tegra186_sec_irqs, - sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); + tegra_gic_setup(tegra186_sec_irqs, (uint32_t)ARRAY_SIZE(tegra186_sec_irqs); /* * Initialize the FIQ handler only if the platform supports any * FIQ interrupt sources. */ - if (sizeof(tegra186_sec_irqs) > 0) + if (sizeof(tegra186_sec_irqs) > 0U) { tegra_fiq_handler_setup(); + } } /******************************************************************************* diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c index 4b6a901db5..38802845d2 100644 --- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c +++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c @@ -18,11 +18,14 @@ #include <tegra_platform.h> #include <stdbool.h> -extern uint32_t tegra186_system_powerdn_state; - extern bool tegra_fake_system_suspend; /******************************************************************************* + * Offset to read the ref_clk counter value + ******************************************************************************/ +#define REF_CLK_OFFSET 4ULL + +/******************************************************************************* * Tegra186 SiP SMCs ******************************************************************************/ #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01 @@ -51,7 +54,7 @@ extern bool tegra_fake_system_suspend; /******************************************************************************* * This function is responsible for handling all T186 SiP calls ******************************************************************************/ -int plat_sip_handler(uint32_t smc_fid, +int32_t plat_sip_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, @@ -60,15 +63,21 @@ int plat_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { - int mce_ret; + int32_t mce_ret, ret = -ENOTSUP; + uint32_t local_smc_fid = smc_fid; + uint64_t local_x1 = x1; + + (void)x4; + (void)cookie; + (void)flags; /* * Convert SMC FID to SMC64 until the linux driver uses * SMC64 encoding. */ - smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); + local_smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); - switch (smc_fid) { + switch (local_smc_fid) { /* * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - @@ -94,18 +103,20 @@ int plat_sip_handler(uint32_t smc_fid, case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: /* clean up the high bits */ - smc_fid &= MCE_CMD_MASK; + local_smc_fid &= MCE_CMD_MASK; /* execute the command and store the result */ mce_ret = mce_command_handler(smc_fid, x1, x2, x3); - write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); + write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, (uint64_t)mce_ret); - return 0; + ret = 0; + break; case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: /* clean up the high bits */ - x1 = (uint32_t)x1; + local_x1 = (uint32_t)x1; + (void)local_x1; /* * SC8 is a special Tegra186 system state where the CPUs and @@ -113,7 +124,8 @@ int plat_sip_handler(uint32_t smc_fid, * alive. */ - return 0; + ret = 0; + break; case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: /* @@ -126,7 +138,7 @@ int plat_sip_handler(uint32_t smc_fid, if (tegra_platform_is_virt_dev_kit()) { tegra_fake_system_suspend = true; - return 0; + ret = 0; } break; @@ -135,5 +147,5 @@ int plat_sip_handler(uint32_t smc_fid, break; } - return -ENOTSUP; + return ret; } diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c index ccdf7f81dc..8913a0117a 100644 --- a/plat/nvidia/tegra/soc/t194/plat_smmu.c +++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c @@ -16,7 +16,7 @@ static uint32_t tegra_misc_read_32(uint32_t off) { - return mmio_read_32(TEGRA_MISC_BASE + off); + return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); } /******************************************************************************* @@ -417,7 +417,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = { smmu_regs_t *plat_get_smmu_ctx(void) { /* index of _END_OF_TABLE_ */ - tegra194_smmu_context[0].val = ARRAY_SIZE(tegra194_smmu_context) - 1; + tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U; return tegra194_smmu_context; } |