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author | Manish Pandey <manish.pandey2@arm.com> | 2021-07-26 11:05:39 +0200 |
---|---|---|
committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2021-07-26 11:05:39 +0200 |
commit | a52c52477aa797e6a261215e9b3536533590b334 (patch) | |
tree | fe42b1908403e23192da125bef7ef05afb9534a0 | |
parent | 76cce57108d782b35a66e8ee5f3baf51193be352 (diff) | |
parent | b5863cab9adb3fed0c1e4dfb92cf906794e7bdb4 (diff) | |
download | trusted-firmware-a-a52c52477aa797e6a261215e9b3536533590b334.tar.gz |
Merge changes from topic "sve+amu" into integration
* changes:
fix(plat/tc0): enable AMU extension
fix(el3_runtime): fix SVE and AMU extension enablement flags
-rw-r--r-- | include/lib/extensions/amu.h | 5 | ||||
-rw-r--r-- | lib/el3_runtime/aarch64/context.S | 7 | ||||
-rw-r--r-- | lib/el3_runtime/aarch64/context_mgmt.c | 37 | ||||
-rw-r--r-- | lib/extensions/amu/aarch64/amu.c | 9 | ||||
-rw-r--r-- | lib/extensions/sve/sve.c | 4 | ||||
-rw-r--r-- | plat/arm/board/tc0/platform.mk | 2 |
6 files changed, 40 insertions, 24 deletions
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h index 3a70e4ffef..3a254c9b10 100644 --- a/include/lib/extensions/amu.h +++ b/include/lib/extensions/amu.h @@ -13,6 +13,7 @@ #include <lib/cassert.h> #include <lib/utils_def.h> +#include <context.h> #include <platform_def.h> /* All group 0 counters */ @@ -80,7 +81,11 @@ struct amu_ctx { }; unsigned int amu_get_version(void); +#if __aarch64__ +void amu_enable(bool el2_unused, cpu_context_t *ctx); +#else void amu_enable(bool el2_unused); +#endif /* Group 0 configuration helpers */ uint64_t amu_group0_cnt_read(unsigned int idx); diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index d610fd4923..40e7ddfa1a 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -903,16 +903,11 @@ func el3_exit #if IMAGE_BL31 /* ---------------------------------------------------------- - * Restore CPTR_EL3, ZCR_EL3 for SVE support. - * If SVE is not supported - skip the restoration. + * Restore CPTR_EL3. * ZCR is only restored if SVE is supported and enabled. * Synchronization is required before zcr_el3 is addressed. * ---------------------------------------------------------- */ - mrs x17, id_aa64pfr0_el1 - ubfx x17, x17, ID_AA64PFR0_SVE_SHIFT, ID_AA64PFR0_SVE_LENGTH - cbz x17, sve_not_enabled - ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3] msr cptr_el3, x19 diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 7a25151c58..7c6f953b26 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -25,6 +25,7 @@ #include <lib/extensions/twed.h> #include <lib/utils.h> +static void enable_extensions_secure(cpu_context_t *ctx); /******************************************************************************* * Context management library initialisation routine. This library is used by @@ -178,19 +179,13 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * indicated by the interrupt routing model for BL31. */ scr_el3 |= get_scr_el3_from_routing_model(security_state); - -#if ENABLE_SVE_FOR_NS - if (security_state == NON_SECURE) { - sve_enable(ctx); - } #endif -#if ENABLE_SVE_FOR_SWD + + /* Save the initialized value of CPTR_EL3 register */ + write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); if (security_state == SECURE) { - sve_enable(ctx); + enable_extensions_secure(ctx); } -#endif - -#endif /* * SCR_EL3.HCE: Enable HVC instructions if next execution state is @@ -335,7 +330,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise * it is zero. ******************************************************************************/ -static void enable_extensions_nonsecure(bool el2_unused) +static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) { #if IMAGE_BL31 #if ENABLE_SPE_FOR_LOWER_ELS @@ -343,7 +338,11 @@ static void enable_extensions_nonsecure(bool el2_unused) #endif #if ENABLE_AMU - amu_enable(el2_unused); + amu_enable(el2_unused, ctx); +#endif + +#if ENABLE_SVE_FOR_NS + sve_enable(ctx); #endif #if ENABLE_MPAM_FOR_LOWER_ELS @@ -353,6 +352,18 @@ static void enable_extensions_nonsecure(bool el2_unused) } /******************************************************************************* + * Enable architecture extensions on first entry to Secure world. + ******************************************************************************/ +static void enable_extensions_secure(cpu_context_t *ctx) +{ +#if IMAGE_BL31 +#if ENABLE_SVE_FOR_SWD + sve_enable(ctx); +#endif +#endif +} + +/******************************************************************************* * The following function initializes the cpu_context for a CPU specified by * its `cpu_idx` for first use, and sets the initial entrypoint state as * specified by the entry_point_info structure. @@ -586,7 +597,7 @@ void cm_prepare_el3_exit(uint32_t security_state) write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); } - enable_extensions_nonsecure(el2_unused); + enable_extensions_nonsecure(el2_unused, ctx); } cm_el1_sysregs_context_restore(security_state); diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c index 24c3737b7f..295c0d569c 100644 --- a/lib/extensions/amu/aarch64/amu.c +++ b/lib/extensions/amu/aarch64/amu.c @@ -46,7 +46,7 @@ bool amu_group1_supported(void) * Enable counters. This function is meant to be invoked * by the context management library before exiting from EL3. */ -void amu_enable(bool el2_unused) +void amu_enable(bool el2_unused, cpu_context_t *ctx) { uint64_t v; unsigned int amu_version = amu_get_version(); @@ -88,12 +88,13 @@ void amu_enable(bool el2_unused) } /* - * CPTR_EL3.TAM: Set to zero so that any accesses to + * Retrieve and update the CPTR_EL3 value from the context mentioned + * in 'ctx'. Set CPTR_EL3.TAM to zero so that any accesses to * the Activity Monitor registers do not trap to EL3. */ - v = read_cptr_el3(); + v = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); v &= ~TAM_BIT; - write_cptr_el3(v); + write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, v); /* Enable group 0 counters */ write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK); diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c index 7043cc220d..2702c30f31 100644 --- a/lib/extensions/sve/sve.c +++ b/lib/extensions/sve/sve.c @@ -27,11 +27,13 @@ static bool sve_supported(void) void sve_enable(cpu_context_t *context) { + u_register_t cptr_el3; + if (!sve_supported()) { return; } - u_register_t cptr_el3 = read_cptr_el3(); + cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); /* Enable access to SVE functionality for all ELs. */ cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk index 814ccd3482..5ae87d1778 100644 --- a/plat/arm/board/tc0/platform.mk +++ b/plat/arm/board/tc0/platform.mk @@ -114,6 +114,8 @@ override CTX_INCLUDE_PAUTH_REGS := 1 override ENABLE_SPE_FOR_LOWER_ELS := 0 +override ENABLE_AMU := 1 + include plat/arm/common/arm_common.mk include plat/arm/css/common/css_common.mk include plat/arm/soc/common/soc_css.mk |