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authorSieu Mun Tang <sieu.mun.tang@intel.com>2022-07-01 09:08:57 +0800
committerSandrine Bailleux <sandrine.bailleux@arm.com>2022-11-21 13:50:10 +0100
commit8e53b2fa2eef44457ae1b50cd116e13d67df35f8 (patch)
tree3c6a9ab6226f3c3d400f58c4acd7e8691caaaedd
parent8613c157549a28c216fbc22ce66e8e47f1d0d2f8 (diff)
downloadtrusted-firmware-a-8e53b2fa2eef44457ae1b50cd116e13d67df35f8.tar.gz
fix(intel): fix UART baud rate and clock
Revise the UART baud rate and clock for general platform build, SIMIC build and EMU build. Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353
-rw-r--r--plat/intel/soc/agilex/platform.mk1
-rw-r--r--plat/intel/soc/common/include/platform_def.h11
-rw-r--r--plat/intel/soc/n5x/platform.mk1
-rw-r--r--plat/intel/soc/stratix10/platform.mk1
4 files changed, 5 insertions, 9 deletions
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index ccb4e071f0..a1e58fcca8 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -80,5 +80,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
-SIMICS_BUILD := 0
USE_COHERENT_MEM := 1
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index a31adf707e..2b3f144cac 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -17,6 +17,7 @@
#define PLAT_SOCFPGA_STRATIX10 1
#define PLAT_SOCFPGA_AGILEX 2
#define PLAT_SOCFPGA_N5X 3
+#define PLAT_SOCFPGA_EMULATOR 0
/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
#define PLAT_CPU_RELEASE_ADDR 0xffd12210
@@ -170,14 +171,12 @@
#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE
-#ifndef SIMICS_BUILD
-#define PLAT_BAUDRATE (115200)
-#define PLAT_UART_CLOCK (100000000)
-
-#else
+#if PLAT_SOCFPGA_EMULATOR
#define PLAT_BAUDRATE (4800)
#define PLAT_UART_CLOCK (76800)
-
+#else
+#define PLAT_BAUDRATE (115200)
+#define PLAT_UART_CLOCK (100000000)
#endif
/*******************************************************************************
diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk
index 953bf0caf7..be1ad8c6b6 100644
--- a/plat/intel/soc/n5x/platform.mk
+++ b/plat/intel/soc/n5x/platform.mk
@@ -49,5 +49,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
-SIMICS_BUILD := 0
USE_COHERENT_MEM := 1
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 5c0b421468..b7eb4bd775 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -77,5 +77,4 @@ BL31_SOURCES += \
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
-SIMICS_BUILD := 0
USE_COHERENT_MEM := 1