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authorAndré Przywara <andre.przywara@arm.com>2021-07-26 17:29:30 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-07-26 17:29:30 +0200
commit81e63f25ff2414385cb7ce24db47d5f39a0ccbb3 (patch)
tree647d8f50d0f2267f50ca5031688379bbe6daa0df
parentf98c0bea9c31630fce4895b8ae2fc50e399fe9ec (diff)
parent0e54a7899dcab939e5204bbe52dc29b9674cfd13 (diff)
downloadtrusted-firmware-a-81e63f25ff2414385cb7ce24db47d5f39a0ccbb3.tar.gz
Merge changes from topic "allwinner_mmap" into integration
* changes: refactor(plat/allwinner): clean up platform definitions refactor(plat/allwinner): do not map BL32 DRAM at EL3 refactor(plat/allwinner): map SRAM as device memory by default refactor(plat/allwinner): rename static mmap region constant feat(bl_common): import BL_NOBITS_{BASE,END} when defined
-rw-r--r--include/common/bl_common.h4
-rw-r--r--plat/allwinner/common/include/platform_def.h20
-rw-r--r--plat/allwinner/common/sunxi_common.c22
-rw-r--r--plat/allwinner/common/sunxi_scpi_pm.c1
-rw-r--r--plat/allwinner/sun50i_a64/sunxi_power.c1
5 files changed, 27 insertions, 21 deletions
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 77fb1f679e..e33840c9d1 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -106,6 +106,10 @@ IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END);
IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END);
#endif
+#if SEPARATE_NOBITS_REGION
+IMPORT_SYM(uintptr_t, __NOBITS_START__, BL_NOBITS_BASE);
+IMPORT_SYM(uintptr_t, __NOBITS_END__, BL_NOBITS_END);
+#endif
IMPORT_SYM(uintptr_t, __RW_END__, BL_END);
#if defined(IMAGE_BL1)
diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
index 4893368c26..56a2ad6f78 100644
--- a/plat/allwinner/common/include/platform_def.h
+++ b/plat/allwinner/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,9 +13,6 @@
#include <sunxi_mmap.h>
-/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
-#define SUNXI_SCP_SIZE 0x4000
-
#ifdef SUNXI_BL31_IN_DRAM
#define BL31_BASE SUNXI_DRAM_BASE
@@ -31,7 +28,6 @@
#define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000)
#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \
SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
-#define SUNXI_SCP_BASE BL31_LIMIT
/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
@@ -39,12 +35,14 @@
#define MAX_XLAT_TABLES 1
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
-#define SUNXI_BL33_VIRT_BASE (SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE)
-#endif /* SUNXI_BL31_IN_DRAM */
+#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE
-/* How much memory to reserve as secure for BL32, if configured */
-#define SUNXI_DRAM_SEC_SIZE (32U << 20)
+/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
+#define SUNXI_SCP_BASE BL31_LIMIT
+#define SUNXI_SCP_SIZE 0x4000
+
+#endif /* SUNXI_BL31_IN_DRAM */
/* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
#define SUNXI_DRAM_MAP_SIZE (64U << 20)
@@ -52,7 +50,8 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-#define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS)
+#define MAX_STATIC_MMAP_REGIONS 3
+#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
@@ -72,7 +71,6 @@
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_MAX_CPUS_PER_CLUSTER)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
-#define PLATFORM_MMAP_REGIONS 5
#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
#ifndef SPD_none
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index d47d3605b9..82410b1edf 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,17 +14,11 @@
#include <sunxi_mmap.h>
#include <sunxi_private.h>
-static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
+static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
- MT_RW_DATA | MT_SECURE),
-#ifdef SUNXI_SCP_BASE
- MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
-#endif
MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
- MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
- MT_RW_DATA | MT_SECURE),
MAP_REGION(PRELOADED_BL33_BASE, SUNXI_BL33_VIRT_BASE,
SUNXI_DRAM_MAP_SIZE, MT_RW_DATA | MT_NS),
{},
@@ -40,12 +34,24 @@ void sunxi_configure_mmu_el3(int flags)
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
+ mmap_add_region(BL_CODE_END, BL_CODE_END,
+ BL_END - BL_CODE_END,
+ MT_RW_DATA | MT_SECURE);
+#if SEPARATE_CODE_AND_RODATA
mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
BL_RO_DATA_END - BL_RO_DATA_BASE,
MT_RO_DATA | MT_SECURE);
+#endif
+#if SEPARATE_NOBITS_REGION
+ mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
+ BL_NOBITS_END - BL_NOBITS_BASE,
+ MT_RW_DATA | MT_SECURE);
+#endif
+#if USE_COHERENT_MEM
mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
+#endif
mmap_add(sunxi_mmap);
init_xlat_tables();
diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
index 74763ef7ed..eb37daa636 100644
--- a/plat/allwinner/common/sunxi_scpi_pm.c
+++ b/plat/allwinner/common/sunxi_scpi_pm.c
@@ -212,7 +212,6 @@ int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
uint32_t offset = SUNXI_SCP_BASE - vector;
mmio_write_32(vector, offset >> 2);
- clean_dcache_range(vector, sizeof(uint32_t));
}
/* Take the SCP out of reset. */
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
index 0fdb62d057..a35b9ddc03 100644
--- a/plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -244,7 +244,6 @@ void sunxi_cpu_power_off_self(void)
* in instruction granularity (32 bits).
*/
mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
- clean_dcache_range(arisc_reset_vec, 4);
/* De-assert the arisc reset line to let it run. */
mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));