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authorSteven Kao <skao@nvidia.com>2017-08-16 20:12:00 +0800
committerVarun Wadekar <vwadekar@nvidia.com>2019-11-28 11:14:21 -0800
commit72e8caa7467e72134e45cb769b6dab39daf6b3c3 (patch)
treee9c04f0f73b77f04fcfbeff5c9b1f44b94065d89
parentf32e852596704f517d7804693d056914fb52a0e3 (diff)
downloadtrusted-firmware-a-72e8caa7467e72134e45cb769b6dab39daf6b3c3.tar.gz
Tegra194: update cache operations supported by the ROC
This patch updates the cache ops to use system registers in order to trigger cache flush/clean operations. Change-Id: I888abad22f22b8a33c7193b991fad8c4a78030d0 Signed-off-by: Steven Kao <skao@nvidia.com>
-rw-r--r--plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h3
-rw-r--r--plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S21
-rw-r--r--plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c57
3 files changed, 62 insertions, 19 deletions
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 3ac5333a04..415dc0f89a 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -75,5 +75,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
void nvg_set_request_data(uint64_t req, uint64_t data);
void nvg_set_request(uint64_t req);
uint64_t nvg_get_result(void);
+uint64_t nvg_cache_clean(void);
+uint64_t nvg_cache_clean_inval(void);
+uint64_t nvg_cache_inval_all(void);
#endif /* __MCE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
index e6a6a99802..3c47208a10 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
@@ -10,6 +10,9 @@
.globl nvg_set_request_data
.globl nvg_set_request
.globl nvg_get_result
+ .globl nvg_cache_clean
+ .globl nvg_cache_clean_inval
+ .globl nvg_cache_inval_all
/* void nvg_set_request_data(uint64_t req, uint64_t data) */
func nvg_set_request_data
@@ -29,3 +32,21 @@ func nvg_get_result
mrs x0, s3_0_c15_c1_3
ret
endfunc nvg_get_result
+
+/* uint64_t nvg_cache_clean(void) */
+func nvg_cache_clean
+ mrs x0, s3_0_c15_c3_5
+ ret
+endfunc nvg_cache_clean
+
+/* uint64_t nvg_cache_clean_inval(void) */
+func nvg_cache_clean_inval
+ mrs x0, s3_0_c15_c3_6
+ ret
+endfunc nvg_cache_clean_inval
+
+/* uint64_t nvg_cache_inval_all(void) */
+func nvg_cache_inval_all
+ mrs x0, s3_0_c15_c3_7
+ ret
+endfunc nvg_cache_inval_all \ No newline at end of file
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index c7f6591866..2eba1d33e0 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -15,10 +15,8 @@
#include <t194_nvg.h>
#include <tegra_private.h>
-extern void nvg_set_request_data(uint64_t req, uint64_t data);
-extern void nvg_set_request(uint64_t req);
-extern uint64_t nvg_get_result(void);
-
+#define ID_AFR0_EL1_CACHE_OPS_SHIFT 12
+#define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU
/*
* Reports the major and minor version of this interface.
*
@@ -306,41 +304,62 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
/*
* Cache clean operation for all CCPLEX caches.
- *
- * NVGDATA[0] cache_clean
*/
int32_t nvg_roc_clean_cache(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
- (uint64_t)CACHE_CLEAN_SET);
+ int32_t ret = 0;
- return 0;
+ /* check if cache flush through mts is supported */
+ if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+ ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+ if (nvg_cache_clean() == 0U) {
+ ERROR("%s: failed\n", __func__);
+ ret = EINVAL;
+ }
+ } else {
+ ret = EINVAL;
+ }
+ return ret;
}
/*
* Cache clean and invalidate operation for all CCPLEX caches.
- *
- * NVGDATA[1] cache_clean_inval
*/
int32_t nvg_roc_flush_cache(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
- (uint64_t)CACHE_CLEAN_INVAL_SET);
+ int32_t ret = 0;
- return 0;
+ /* check if cache flush through mts is supported */
+ if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+ ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+ if (nvg_cache_clean_inval() == 0U) {
+ ERROR("%s: failed\n", __func__);
+ ret = EINVAL;
+ }
+ } else {
+ ret = EINVAL;
+ }
+ return ret;
}
/*
* Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
- *
- * NVGDATA[2] cache_clean_inval_tr
*/
int32_t nvg_roc_clean_cache_trbits(void)
{
- nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
- (uint64_t)CACHE_CLEAN_INVAL_TR_SET);
+ int32_t ret = 0;
- return 0;
+ /* check if cache flush through mts is supported */
+ if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+ ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+ if (nvg_cache_inval_all() == 0U) {
+ ERROR("%s: failed\n", __func__);
+ ret = EINVAL;
+ }
+ } else {
+ ret = EINVAL;
+ }
+ return ret;
}
/*