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authorRoger Lu <roger.lu@mediatek.com>2021-06-24 15:17:48 +0800
committerroger.lu <roger.lu@mediatek.com>2021-07-21 03:36:14 +0200
commit310c3a26e17d99aafc73b3504d0b6dfbdb97fd4c (patch)
tree2b0c44eedd19844988505bf276866ff10650ff9d
parente2a16044ad8ef33c7ce6e2c72c882d05583e1c38 (diff)
downloadtrusted-firmware-a-310c3a26e17d99aafc73b3504d0b6dfbdb97fd4c.tar.gz
fix(mediatek/mt8192/spm): add missing bit define for debug purpose
Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I6dbf6d4ea6310c3371ca15d1e7cce249a05af2fb
-rw-r--r--plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c5
-rw-r--r--plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h19
2 files changed, 10 insertions, 14 deletions
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
index 307862dbf6..2d67fdf512 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
@@ -143,6 +143,11 @@ unsigned int mt_spm_cond_check(int state_id,
blocked |= SPM_COND_CHECK_BLOCKED_PLL;
}
+ if (is_system_suspend && (blocked != 0U)) {
+ INFO("suspend: %s total blocked = 0x%08x\n",
+ dest->name, blocked);
+ }
+
return blocked;
}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
index ba13fe37cc..91ebdd94f8 100644
--- a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
@@ -23,20 +23,11 @@ enum PLAT_SPM_COND {
PLAT_SPM_COND_MAX,
};
-enum PLAT_SPM_COND_PLL {
- PLAT_SPM_COND_PLL_UNIVPLL = 0,
- PLAT_SPM_COND_PLL_MFGPLL,
- PLAT_SPM_COND_PLL_MSDCPLL,
- PLAT_SPM_COND_PLL_TVDPLL,
- PLAT_SPM_COND_PLL_MMPLL,
- PLAT_SPM_COND_PLL_MAX,
-};
-
-#define PLL_BIT_MFGPLL (PLAT_SPM_COND_PLL_MFGPLL)
-#define PLL_BIT_MMPLL (PLAT_SPM_COND_PLL_MMPLL)
-#define PLL_BIT_UNIVPLL (PLAT_SPM_COND_PLL_UNIVPLL)
-#define PLL_BIT_MSDCPLL (PLAT_SPM_COND_PLL_MSDCPLL)
-#define PLL_BIT_TVDPLL (PLAT_SPM_COND_PLL_TVDPLL)
+#define PLL_BIT_UNIVPLL BIT(0)
+#define PLL_BIT_MFGPLL BIT(1)
+#define PLL_BIT_MSDCPLL BIT(2)
+#define PLL_BIT_TVDPLL BIT(3)
+#define PLL_BIT_MMPLL BIT(4)
/* Definition about SPM_COND_CHECK_BLOCKED
* bit [00 ~ 15]: cg blocking index