diff options
author | Steven Kao <skao@nvidia.com> | 2017-09-29 18:09:17 +0800 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-11-28 11:14:21 -0800 |
commit | 2bda92025bbc72f35b4a1bee76cfb1a2b002e5e6 (patch) | |
tree | 45664572403f0fceb0848ebf012920a2cdf46d25 | |
parent | 72e8caa7467e72134e45cb769b6dab39daf6b3c3 (diff) | |
download | trusted-firmware-a-2bda92025bbc72f35b4a1bee76cfb1a2b002e5e6.tar.gz |
Tegra194: update nvg header to v6.1
This patch updates t194_nvg.h to v6.1 and does not issue NVG
commands for unsupported platforms.
Change-Id: I506b594a70a3651d01a412ab79b3c8919b1d66f1
Signed-off-by: Steven Kao <skao@nvidia.com>
-rw-r--r-- | plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h | 288 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/drivers/mce/mce.c | 56 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c | 18 |
3 files changed, 215 insertions, 147 deletions
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h index 1fe462032d..5a72680acd 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h +++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h @@ -20,77 +20,82 @@ */ enum { TEGRA_NVG_VERSION_MAJOR = 6, - TEGRA_NVG_VERSION_MINOR = 0, + TEGRA_NVG_VERSION_MINOR = 1 }; typedef enum { - TEGRA_NVG_CHANNEL_VERSION = 0, - TEGRA_NVG_CHANNEL_POWER_PERF = 1, - TEGRA_NVG_CHANNEL_POWER_MODES = 2, - TEGRA_NVG_CHANNEL_WAKE_TIME = 3, - TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, - TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, - TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, - // Value 7 reserved - TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, - // Value 9 reserved - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, - TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, - // Values 12-42 reserved - TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, - TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, - TEGRA_NVG_CHANNEL_CC3_CTRL = 45, - TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, - TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51, - // 52 FREQ FEEDBACK - TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, - TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, - TEGRA_NVG_CHANNEL_LAST_INDEX, + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_POWER_PERF = 1, + TEGRA_NVG_CHANNEL_POWER_MODES = 2, + TEGRA_NVG_CHANNEL_WAKE_TIME = 3, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, + TEGRA_NVG_CHANNEL_SHUTDOWN = 42, + TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, + TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, + TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, + TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, + TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, + TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, + TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 60, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 61, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 62, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 63, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 64, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 65, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 66, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 67, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 68, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 69, + TEGRA_NVG_CHANNEL_LAST_INDEX } tegra_nvg_channel_id_t; - typedef enum { - // Value 0 reserved - NVG_STAT_QUERY_SC7_ENTRIES = 1, - // Values 2-5 reserved - NVG_STAT_QUERY_CC6_ENTRIES = 6, - NVG_STAT_QUERY_CG7_ENTRIES = 7, - // Values 8-9 reserved - NVG_STAT_QUERY_C6_ENTRIES = 10, - // Values 11-13 reserved - NVG_STAT_QUERY_C7_ENTRIES = 14, - // Values 15-31 reserved + NVG_STAT_QUERY_SC7_ENTRIES = 1, + NVG_STAT_QUERY_CC6_ENTRIES = 6, + NVG_STAT_QUERY_CG7_ENTRIES = 7, + NVG_STAT_QUERY_C6_ENTRIES = 10, + NVG_STAT_QUERY_C7_ENTRIES = 14, NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, - NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, - NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, + NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, + NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56 } tegra_nvg_stat_query_t; - typedef enum { TEGRA_NVG_CORE_C0 = 0, TEGRA_NVG_CORE_C1 = 1, TEGRA_NVG_CORE_C6 = 6, TEGRA_NVG_CORE_C7 = 7, - TEGRA_NVG_CORE_WARMRSTREQ = 8, + TEGRA_NVG_CORE_WARMRSTREQ = 8 } tegra_nvg_core_sleep_state_t; typedef enum { TEGRA_NVG_CLUSTER_CC0 = 0, - TEGRA_NVG_CLUSTER_CC6 = 6, + TEGRA_NVG_CLUSTER_CC6 = 6 } tegra_nvg_cluster_sleep_state_t; typedef enum { - TEGRA_NVG_CCPLEX_CG0 = 0, - TEGRA_NVG_CCPLEX_CG7 = 1, + TEGRA_NVG_CG_CG0 = 0, + TEGRA_NVG_CG_CG7 = 1 } tegra_nvg_cluster_group_sleep_state_t; typedef enum { TEGRA_NVG_SYSTEM_SC0 = 0, TEGRA_NVG_SYSTEM_SC7 = 7, - TEGRA_NVG_SYSTEM_SC8 = 8, + TEGRA_NVG_SYSTEM_SC8 = 8 } tegra_nvg_system_sleep_state_t; // --------------------------------------------------------------------------- @@ -111,19 +116,33 @@ typedef union nvg_channel_1_data_u uint64_t flat; struct nvg_channel_1_data_s { - uint64_t perf_per_watt_mode : 1; - uint64_t reserved_63_1 : 63; + uint32_t perf_per_watt_mode : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; } bits; } nvg_channel_1_data_t; +typedef union +{ + uint64_t flat; + struct nvg_ccplex_cache_control_channel_t { + uint32_t gpu_ways : 5; + uint32_t reserved_7_5 : 3; + uint32_t gpu_only_ways : 5; + uint32_t reserved_31_13 : 19; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_ccplex_cache_control_channel_t; + typedef union nvg_channel_2_data_u { uint64_t flat; struct nvg_channel_2_data_s { - uint64_t reserved_1_0 : 2; - uint64_t battery_saver_mode : 1; - uint64_t reserved_63_3 : 61; + uint32_t reserved_1_0 : 2; + uint32_t battery_saver_mode : 1; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; } bits; } nvg_channel_2_data_t; @@ -131,8 +150,8 @@ typedef union { uint64_t flat; struct nvg_wake_time_channel_t { - uint64_t wake_time : 32; - uint64_t reserved_63_32 : 32; + uint32_t wake_time : 32; + uint32_t reserved_63_32 : 32; } bits; } nvg_wake_time_channel_t; @@ -140,18 +159,18 @@ typedef union { uint64_t flat; struct nvg_cstate_info_channel_t { - uint64_t cluster_state : 3; - uint64_t reserved_6_3 : 4; - uint64_t update_cluster : 1; - uint64_t cg_cstate : 3; - uint64_t reserved_14_11 : 4; - uint64_t update_cg : 1; - uint64_t system_cstate : 4; - uint64_t reserved_22_20 : 3; - uint64_t update_system : 1; - uint64_t reserved_30_24 : 7; - uint64_t update_wake_mask : 1; - uint64_t wake_mask : 32; + uint32_t cluster_state : 3; + uint32_t reserved_6_3 : 4; + uint32_t update_cluster : 1; + uint32_t cg_cstate : 3; + uint32_t reserved_14_11 : 4; + uint32_t update_cg : 1; + uint32_t system_cstate : 4; + uint32_t reserved_22_20 : 3; + uint32_t update_system : 1; + uint32_t reserved_30_24 : 7; + uint32_t update_wake_mask : 1; + uint32_t wake_mask : 32; } bits; } nvg_cstate_info_channel_t; @@ -159,20 +178,19 @@ typedef union { uint64_t flat; struct nvg_lower_bound_channel_t { - uint64_t crossover_value : 32; - uint64_t reserved_63_32 : 32; + uint32_t crossover_value : 32; + uint32_t reserved_63_32 : 32; } bits; } nvg_lower_bound_channel_t; - typedef union { uint64_t flat; struct nvg_cstate_stat_query_channel_t { - uint64_t unit_id : 4; - uint64_t reserved_15_4 : 12; - uint64_t stat_id : 16; - uint64_t reserved_63_32 : 32; + uint32_t unit_id : 4; + uint32_t reserved_15_4 : 12; + uint32_t stat_id : 16; + uint32_t reserved_63_32 : 32; } bits; } nvg_cstate_stat_query_channel_t; @@ -180,96 +198,102 @@ typedef union { uint64_t flat; struct nvg_is_sc7_allowed_channel_t { - uint64_t is_sc7_allowed : 1; - uint64_t reserved_63_32 : 63; + uint32_t is_sc7_allowed : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; } bits; } nvg_is_sc7_allowed_channel_t; - typedef union { uint64_t flat; struct nvg_core_online_channel_t { - uint64_t core_id : 4; - uint64_t reserved_63_4 : 60; + uint32_t core_id : 4; + uint32_t reserved_31_4 : 28; + uint32_t reserved_63_32 : 32; } bits; } nvg_core_online_channel_t; - typedef union { uint64_t flat; struct nvg_cc3_control_channel_t { - uint64_t freq_req : 8; - uint64_t reserved_30_8 : 23; - uint64_t enable : 1; - uint64_t reserved_63_32 : 32; + uint32_t freq_req : 8; + uint32_t reserved_30_8 : 23; + uint32_t enable : 1; + uint32_t reserved_63_32 : 32; } bits; } nvg_cc3_control_channel_t; +typedef enum { + TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9 , + TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, + TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, + TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, + TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, + TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, + TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, + TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, + TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX +} tegra_nvg_channel_update_gsc_gsc_enum_t; typedef union { uint64_t flat; - struct nvg_update_gsc_channel_t { - uint64_t gsc_enum : 16; - uint64_t reserved_63_16 : 48; + struct nvg_update_ccplex_gsc_channel_t { + uint32_t gsc_enum : 16; + uint32_t reserved_31_16 : 16; + uint32_t reserved_63_32 : 32; } bits; -} nvg_update_gsc_channel_t; - +} nvg_update_ccplex_gsc_channel_t; typedef union { uint64_t flat; - struct nvg_cache_inval_channel_t { - uint64_t cache_clean : 1; - uint64_t cache_clean_inval : 1; - uint64_t cache_clean_inval_tr : 1; - uint64_t reserved_63_3 : 61; + struct nvg_security_config_channel_t { + uint32_t strict_checking_enabled : 1; + uint32_t strict_checking_locked : 1; + uint32_t reserved_31_2 : 30; + uint32_t reserved_63_32 : 32; } bits; -} nvg_cache_inval_channel_t; - +} nvg_security_config_t; -/* GSC type define */ -typedef enum { - TEGRA_NVG_GSC_ALL=0, - TEGRA_NVG_GSC_NVDEC=1, - TEGRA_NVG_GSC_WPR1=2, - TEGRA_NVG_GSC_WPR2=3, - TEGRA_NVG_GSC_TSECA=4, - TEGRA_NVG_GSC_TSECB=5, - - TEGRA_NVG_GSC_BPMP=6, - TEGRA_NVG_GSC_APE=7, - TEGRA_NVG_GSC_SPE=8, - TEGRA_NVG_GSC_SCE=9, - TEGRA_NVG_GSC_APR=10, - TEGRA_NVG_GSC_TZRAM=11, - TEGRA_NVG_GSC_SE=12, - - TEGRA_NVG_GSC_DMCE=13, - TEGRA_NVG_GSC_BPMP_TO_DMCE=14, - TEGRA_NVG_GSC_BPMP_TO_SPE=16, - TEGRA_NVG_GSC_CPU_TZ_TO_BPMP=18, - TEGRA_NVG_GSC_CPU_NS_TO_BPMP=20, - TEGRA_NVG_GSC_IPC_SE_SPE_SCE_BPMP=22, - TEGRA_NVG_GSC_SC7_RESUME_FW=23, - - TEGRA_NVG_GSC_VPR_RESIZE=24, - TEGRA_NVG_GSC_RCE=25, - TEGRA_NVG_GSC_CV=26, - - TEGRA_NVG_GSC_BO_MTS_PACKAGE=28, - TEGRA_NVG_GSC_BO_MCE_PREBOOT=29, - - TEGRA_NVG_GSC_TZ_DRAM_IDX=34, - TEGRA_NVG_GSC_VPR_IDX=35, -} tegra_nvg_gsc_index_t; - -typedef enum { - TEGRA_NVG_CROSSOVER_C6 = 0, - TEGRA_NVG_CROSSOVER_CC6 = 1, - TEGRA_NVG_CROSSOVER_CG7 = 2, -} tegra_nvg_crossover_index_t; +typedef union +{ + uint64_t flat; + struct nvg_shutdown_channel_t { + uint32_t reboot : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_shutdown_t; -#endif // T194_NVG_H +#endif diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c index 0a6515e1ce..355a5474e3 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c @@ -16,12 +16,25 @@ #include <mce_private.h> #include <mmio.h> #include <platform_def.h> +#include <stdbool.h> #include <string.h> #include <errno.h> #include <t194_nvg.h> #include <tegra_def.h> #include <tegra_platform.h> +/* Handler to check if MCE firmware is supported */ +static bool mce_firmware_not_supported(void) +{ + bool status; + + /* these platforms do not load MCE firmware */ + status = tegra_platform_is_linsim() || tegra_platform_is_qt() || + tegra_platform_is_virt_dev_kit(); + + return status; +} + /******************************************************************************* * Common handler for all MCE commands ******************************************************************************/ @@ -174,7 +187,18 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, ******************************************************************************/ int32_t mce_update_gsc_videomem(void) { - return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX); + int32_t ret; + + /* + * MCE firmware is not running on simulation platforms. + */ + if (mce_firmware_not_supported()) { + ret = -EINVAL; + } else { + ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR); + } + + return ret; } /******************************************************************************* @@ -182,7 +206,18 @@ int32_t mce_update_gsc_videomem(void) ******************************************************************************/ int32_t mce_update_gsc_tzdram(void) { - return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX); + int32_t ret; + + /* + * MCE firmware is not running on simulation platforms. + */ + if (mce_firmware_not_supported()) { + ret = -EINVAL; + } else { + ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM); + } + + return ret; } /******************************************************************************* @@ -190,7 +225,18 @@ int32_t mce_update_gsc_tzdram(void) ******************************************************************************/ int32_t mce_update_gsc_tzram(void) { - return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM); + int32_t ret; + + /* + * MCE firmware is not running on simulation platforms. + */ + if (mce_firmware_not_supported()) { + ret = -EINVAL; + } else { + ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM); + } + + return ret; } /******************************************************************************* @@ -215,9 +261,7 @@ void mce_verify_firmware_version(void) /* * MCE firmware is not running on simulation platforms. */ - if ((tegra_platform_is_linsim() == 1U) || - (tegra_platform_is_virt_dev_kit() == 1U) || - (tegra_platform_is_qt() == 1U)) { + if (mce_firmware_not_supported()) { return; } diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c index 2eba1d33e0..6451f02c5a 100644 --- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c @@ -142,26 +142,26 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex, * Indices gives MTS the crossover point in TSC ticks for when it becomes * no longer viable to enter the named state * - * Type 0 : NVGDATA[0:31]: C6 Lower bound - * Type 1 : NVGDATA[0:31]: CC6 Lower bound - * Type 2 : NVGDATA[0:31]: CG7 Lower bound + * Type 5 : NVGDATA[0:31]: C6 Lower bound + * Type 6 : NVGDATA[0:31]: CC6 Lower bound + * Type 8 : NVGDATA[0:31]: CG7 Lower bound */ int32_t nvg_update_crossover_time(uint32_t type, uint32_t time) { int32_t ret = 0; switch (type) { - case TEGRA_NVG_CROSSOVER_C6: + case TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND: nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CROSSOVER_CC6: + case TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND: nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND, (uint64_t)time); break; - case TEGRA_NVG_CROSSOVER_CG7: + case TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND: nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND, (uint64_t)time); break; @@ -288,11 +288,11 @@ int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable) */ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx) { - int32_t ret = 0; + int32_t ret; /* sanity check GSC ID */ - if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) { - ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx); + if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) { + ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx); ret = EINVAL; } else { nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC, |