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author | Mark Dykes <mark.dykes@arm.com> | 2021-09-09 17:48:48 +0200 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2021-09-09 17:48:48 +0200 |
commit | 20a20538f8e6aa40b91ed596bfe1ff5a123222c4 (patch) | |
tree | 510ca96285c2bee2e654eda9d8bcac159639a1d0 | |
parent | d114a382c7fd795decb4cb65b481b2d86b58b30c (diff) | |
parent | 86b43c58a4105c8cef13d860dd73fa9bd560526a (diff) | |
download | trusted-firmware-a-20a20538f8e6aa40b91ed596bfe1ff5a123222c4.tar.gz |
Merge "feat(fdts): add firewall regions into STM32MP1 DT" into integration
-rw-r--r-- | fdts/stm32mp15-fw-config.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/fdts/stm32mp15-fw-config.dtsi b/fdts/stm32mp15-fw-config.dtsi index 4f2841f8e0..8aece289a7 100644 --- a/fdts/stm32mp15-fw-config.dtsi +++ b/fdts/stm32mp15-fw-config.dtsi @@ -4,9 +4,27 @@ */ #include <common/tbbr/tbbr_img_def.h> +#include <dt-bindings/soc/stm32mp15-tzc400.h> #include <platform_def.h> +#ifndef DDR_SIZE +#error "DDR_SIZE is not defined" +#endif + +#define DDR_NS_BASE STM32MP_DDR_BASE +#ifdef AARCH32_SP_OPTEE +/* OP-TEE reserved shared memory: located at DDR top */ +#define DDR_SHARE_SIZE STM32MP_DDR_SHMEM_SIZE +#define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE)) +/* OP-TEE secure memory: located right below OP-TEE reserved shared memory */ +#define DDR_SEC_SIZE STM32MP_DDR_S_SIZE +#define DDR_SEC_BASE (DDR_SHARE_BASE - DDR_SEC_SIZE) +#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) +#else /* !AARCH32_SP_OPTEE */ +#define DDR_NS_SIZE DDR_SIZE +#endif /* AARCH32_SP_OPTEE */ + /dts-v1/; / { @@ -45,4 +63,18 @@ }; #endif }; + + st-mem-firewall { + compatible = "st,mem-firewall"; +#ifdef AARCH32_SP_OPTEE + memory-ranges = < + DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR + DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0 + DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE + TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID)>; +#else + memory-ranges = < + DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR>; +#endif + }; }; |