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authorMark Dykes <mark.dykes@arm.com>2021-10-14 22:56:25 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-10-14 22:56:25 +0200
commit115901bc2d241070bd7841465d12d5541e6edb0c (patch)
treef4887bccf40c0fe709062fc67e1ffe525b09542d
parentd20d5002f9cb1d2711ca02376d94074b561cdf6e (diff)
parent602ae2f23c2bc9d79a9ab2b7c5dde1932fffc984 (diff)
downloadtrusted-firmware-a-115901bc2d241070bd7841465d12d5541e6edb0c.tar.gz
Merge "fix(stm32mp1_clk): fix MPU clock rate" into integration
-rw-r--r--drivers/st/clk/stm32mp1_clk.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index d1fc57827a..9764a9f2d9 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -850,9 +850,7 @@ static unsigned long get_clock_rate(int p)
reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
clkdiv = reg & RCC_MPUDIV_MASK;
- if (clkdiv != 0U) {
- clock /= stm32mp1_mpu_div[clkdiv];
- }
+ clock >>= stm32mp1_mpu_div[clkdiv];
break;
default:
break;