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/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <sp_res_desc_def.h>
#include "ivy_def.h"
/* 4 KiB pages */
#define PAGE_SIZE U(0x1000)
/*
* FVP platform layout. The defines are hardcoded here because including the
* platform headers have too many dependencies.
* TODO: Move this to the platform layer.
*/
#define V2M_IOFPGA_BASE ULL(0x1c000000)
#define V2M_IOFPGA_SIZE ULL(0x03000000)
/* Aggregate of all devices in the first GB. */
#define DEVICE0_BASE ULL(0x20000000)
#define DEVICE0_SIZE ULL(0x0c200000)
/dts-v1/;
/ {
compatible = "arm,sp_rd";
attribute {
version = <0x00000001>;
sp_type = <RD_ATTR_TYPE_UP_MIGRATABLE>;
pe_mpidr = <0>; /* Unused */
runtime_el = <RD_ATTR_RUNTIME_SEL0>;
exec_type = <RD_ATTR_RUNTIME>;
panic_policy = <RD_ATTR_PANIC_ONESHOT>;
xlat_granule = <RD_ATTR_XLAT_GRANULE_4KB>;
binary_size = <IVY_IMAGE_SIZE>;
load_address = <0x00000000 IVY_IMAGE_BASE>;
entrypoint = <0x00000000 IVY_IMAGE_BASE>;
};
memory_regions {
v2m_iofpga {
str = "V2M IOFPGA";
base = <0x00000000 V2M_IOFPGA_BASE>;
size = <0x00000000 V2M_IOFPGA_SIZE>;
attr = <RD_MEM_DEVICE>;
};
device0 {
str = "Device 0";
base = <0x00000000 DEVICE0_BASE>;
size = <0x00000000 DEVICE0_SIZE>;
attr = <RD_MEM_DEVICE>;
};
spm_buffer {
str = "SPM buffer";
base = <0x00000000 IVY_SPM_BUF_BASE>;
size = <0x00000000 IVY_SPM_BUF_SIZE>;
attr = <RD_MEM_NORMAL_SPM_SP_SHARED_MEM>;
};
ns_buffer {
str = "NS buffer";
base = <0x00000000 IVY_NS_BUF_BASE>;
size = <0x00000000 IVY_NS_BUF_SIZE>;
attr = <RD_MEM_NORMAL_CLIENT_SHARED_MEM>;
};
};
notifications {
notification_0 {
attr = <0>;
pe = <0>;
};
};
services {
test_service_1 {
uuid = <IVY_SERVICE1_UUID_RD>;
accessibility = <(RD_SERV_ACCESS_SECURE |
RD_SERV_ACCESS_EL3 |
RD_SERV_ACCESS_NORMAL)>;
request_type = <(RD_SERV_SUPPORT_BLOCKING |
RD_SERV_SUPPORT_NON_BLOCKING)>;
connection_quota = <10>;
sec_mem_size = <0>;
interrupt_num = <0>;
};
};
};
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