aboutsummaryrefslogtreecommitdiff
path: root/drivers/arm/gic/gic_v3.c
blob: 76b08639c13ce945eca09bd188933e56ee831821 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
/*
 * Copyright (c) 2018, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch.h>
#include <arch_helpers.h>
#include <arm_gic.h>
#include <assert.h>
#include <debug.h>
#include <gic_common.h>
#include <gic_v3.h>
#include <mmio.h>
#include <platform.h>

/* Global variables to store the GIC base addresses */
static uintptr_t gicr_base_addr;
static uintptr_t gicd_base_addr;

#ifndef AARCH32
#define MPIDR_AFFLVL3_MASK	((unsigned long long)MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)
#define gic_typer_affinity_from_mpidr(mpidr)	\
	(((mpidr) & (~MPIDR_AFFLVL3_MASK)) | (((mpidr) & MPIDR_AFFLVL3_MASK) >> 8))
#else
#define gic_typer_affinity_from_mpidr(mpidr)	\
	((mpidr) & ((MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | MPID_MASK))
#endif

/*
 * Data structure to store the GIC per CPU context before entering
 * system suspend. Only the GIC context of first 32 interrupts (SGIs and PPIs)
 * will be saved. The GIC SPI context needs to be restored by the respective
 * drivers.
 */
struct gicv3_pcpu_ctx {
	/* Flag to indicate whether the CPU is suspended */
	unsigned int is_suspended;
	unsigned int icc_igrpen1;
	unsigned int gicr_isenabler;
	unsigned int gicr_ipriorityr[NUM_PCPU_INTR >> IPRIORITYR_SHIFT];
	unsigned int gicr_icfgr;
};

/* Array to store the per-cpu GICv3 context when being suspended.*/
static struct gicv3_pcpu_ctx pcpu_ctx[PLATFORM_CORE_COUNT];

/* Array to store the per-cpu redistributor frame addresses */
static uintptr_t rdist_pcpu_base[PLATFORM_CORE_COUNT];

/*
 * Array to store the mpidr corresponding to each initialized per-CPU
 * redistributor interface.
 */
static unsigned long long mpidr_list[PLATFORM_CORE_COUNT] = {UINT64_MAX};

/******************************************************************************
 * GIC Distributor interface accessors for writing entire registers
 *****************************************************************************/
static void gicd_write_irouter(unsigned int base,
				unsigned int interrupt_id,
				unsigned long long route)
{
	assert(interrupt_id >= MIN_SPI_ID);
	mmio_write_64(base + GICD_IROUTER + (interrupt_id << 3), route);
}

/******************************************************************************
 * GIC Re-distributor interface accessors for writing entire registers
 *****************************************************************************/
static void gicr_write_isenabler0(unsigned int base, unsigned int val)
{
	mmio_write_32(base + GICR_ISENABLER0, val);
}

static void gicr_write_icenabler0(unsigned int base, unsigned int val)
{
	mmio_write_32(base + GICR_ICENABLER0, val);
}

static void gicr_write_icpendr0(unsigned int base, unsigned int val)
{
	mmio_write_32(base + GICR_ICPENDR0, val);
}

static void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
{
	unsigned n = id >> IPRIORITYR_SHIFT;
	mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
}

static void gicr_write_icfgr1(uintptr_t base, unsigned int val)
{
	mmio_write_32(base + GICR_ICFGR1, val);
}

/******************************************************************************
 * GIC Re-distributor interface accessors for reading entire registers
 *****************************************************************************/
static unsigned long long gicr_read_typer(uintptr_t base)
{
	return mmio_read_64(base + GICR_TYPER);
}

static unsigned int gicr_read_icfgr1(uintptr_t base)
{
	return mmio_read_32(base + GICR_ICFGR1);
}

static unsigned int gicr_read_isenabler0(unsigned int base)
{
	return mmio_read_32(base + GICR_ISENABLER0);
}

static unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
{
	unsigned n = id >> IPRIORITYR_SHIFT;
	return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
}

static unsigned int gicr_read_ispendr0(unsigned int base)
{
	return mmio_read_32(base + GICR_ISPENDR0);
}

/******************************************************************************
 * GIC Re-distributor interface accessors for individual interrupt
 * manipulation
 *****************************************************************************/
static unsigned int gicr_get_isenabler0(unsigned int base,
	unsigned int interrupt_id)
{
	unsigned bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1);
	return gicr_read_isenabler0(base) & (1 << bit_num);
}

static void gicr_set_isenabler0(unsigned int base, unsigned int interrupt_id)
{
	unsigned bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1);
	gicr_write_isenabler0(base, (1 << bit_num));
}

static void gicr_set_icenabler0(unsigned int base, unsigned int interrupt_id)
{
	unsigned bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1);
	gicr_write_icenabler0(base, (1 << bit_num));
}

static void gicr_set_icpendr0(unsigned int base, unsigned int interrupt_id)
{
	unsigned bit_num = interrupt_id & ((1 << ICPENDR_SHIFT) - 1);
	gicr_write_icpendr0(base, (1 << bit_num));
}

/******************************************************************************
 * GICv3 public driver API
 *****************************************************************************/
void gicv3_enable_cpuif(void)
{
	/* Assert that system register access is enabled */
	assert(IS_IN_EL2() ? (read_icc_sre_el2() & ICC_SRE_SRE_BIT) :
				(read_icc_sre_el1() & ICC_SRE_SRE_BIT));

	/* Enable Group1 non secure interrupts */
	write_icc_igrpen1_el1(read_icc_igrpen1_el1() | IGRPEN1_EL1_ENABLE_BIT);
	isb();
}

void gicv3_setup_cpuif(void)
{
	/* Set the priority mask register to allow all interrupts to trickle in */
	write_icc_pmr_el1(GIC_PRI_MASK);
	isb();
	gicv3_enable_cpuif();
}

void gicv3_disable_cpuif(void)
{
	/* Disable Group1 non secure interrupts */
	write_icc_igrpen1_el1(read_icc_igrpen1_el1() &
			~IGRPEN1_EL1_ENABLE_BIT);
	isb();
}

void gicv3_save_cpuif_context(void)
{
	unsigned int core_pos = platform_get_core_pos(read_mpidr_el1());

	/* Set the `is_suspended` flag as this core is being suspended. */
	pcpu_ctx[core_pos].is_suspended = 1;
	pcpu_ctx[core_pos].icc_igrpen1 = read_icc_igrpen1_el1();
}

void gicv3_restore_cpuif_context(void)
{
	unsigned int core_pos = platform_get_core_pos(read_mpidr_el1());

	/* Reset the `is_suspended` flag as this core has resumed from suspend. */
	pcpu_ctx[core_pos].is_suspended = 0;
	write_icc_pmr_el1(GIC_PRI_MASK);
	write_icc_igrpen1_el1(pcpu_ctx[core_pos].icc_igrpen1);
	isb();
}

void gicv3_save_sgi_ppi_context(void)
{
	unsigned int i, core_pos;
	unsigned int my_core_pos = platform_get_core_pos(read_mpidr_el1());

	/* Save the context for all the suspended cores */
	for (core_pos = 0; core_pos < PLATFORM_CORE_COUNT; core_pos++) {
		/*
		 * Continue if the core pos is not the current core
		 * and has not suspended
		 */
		if ((core_pos != my_core_pos) &&
				(!pcpu_ctx[core_pos].is_suspended))
			continue;

		assert(rdist_pcpu_base[core_pos]);

		pcpu_ctx[core_pos].gicr_isenabler =
					gicr_read_isenabler0(rdist_pcpu_base[core_pos]);

		/* Read the ipriority registers, 4 at a time */
		for (i = 0; i < (NUM_PCPU_INTR >> IPRIORITYR_SHIFT); i++)
			pcpu_ctx[core_pos].gicr_ipriorityr[i] =
				gicr_read_ipriorityr(rdist_pcpu_base[core_pos],
						i << IPRIORITYR_SHIFT);

		pcpu_ctx[core_pos].gicr_icfgr =
				gicr_read_icfgr1(rdist_pcpu_base[core_pos]);
	}
}

void gicv3_restore_sgi_ppi_context(void)
{
	unsigned int i, core_pos;
	unsigned int my_core_pos = platform_get_core_pos(read_mpidr_el1());

	/* Restore the context for all the suspended cores */
	for (core_pos = 0; core_pos < PLATFORM_CORE_COUNT; core_pos++) {
		/*
		 * Continue if the core pos is not the current core
		 * and has not suspended
		 */
		if ((core_pos != my_core_pos) &&
				(!pcpu_ctx[core_pos].is_suspended))
			continue;

		assert(rdist_pcpu_base[core_pos]);

		/* Read the ipriority registers, 4 at a time */
		for (i = 0; i < (NUM_PCPU_INTR >> IPRIORITYR_SHIFT); i++)
			gicr_write_ipriorityr(rdist_pcpu_base[core_pos],
					i << IPRIORITYR_SHIFT,
					pcpu_ctx[core_pos].gicr_ipriorityr[i]);

		gicr_write_icfgr1(rdist_pcpu_base[core_pos],
				pcpu_ctx[core_pos].gicr_icfgr);
		gicr_write_isenabler0(rdist_pcpu_base[core_pos],
				pcpu_ctx[core_pos].gicr_isenabler);
	}
}

unsigned int gicv3_get_ipriorityr(unsigned int interrupt_id)
{
	unsigned int core_pos;
	assert(gicd_base_addr);
	assert(IS_VALID_INTR_ID(interrupt_id));

	if (interrupt_id < MIN_SPI_ID) {
		core_pos = platform_get_core_pos(read_mpidr_el1());
		assert(rdist_pcpu_base[core_pos]);
		return mmio_read_8(rdist_pcpu_base[core_pos] + GICR_IPRIORITYR
				+ interrupt_id);
	} else {
		return mmio_read_8(gicd_base_addr +
			GICD_IPRIORITYR + interrupt_id);
	}
}

void gicv3_set_ipriorityr(unsigned int interrupt_id,
				unsigned int priority)
{
	unsigned int core_pos;
	assert(gicd_base_addr);
	assert(IS_VALID_INTR_ID(interrupt_id));

	if (interrupt_id < MIN_SPI_ID) {
		core_pos = platform_get_core_pos(read_mpidr_el1());
		assert(rdist_pcpu_base[core_pos]);
		mmio_write_8(rdist_pcpu_base[core_pos] + GICR_IPRIORITYR
				+ interrupt_id, priority & GIC_PRI_MASK);
	} else {
		mmio_write_8(gicd_base_addr + GICD_IPRIORITYR + interrupt_id,
					priority & GIC_PRI_MASK);
	}
}

void gicv3_send_sgi(unsigned int sgi_id, unsigned int core_pos)
{
	unsigned long long aff0, aff1, aff2;
	unsigned long long sgir, target_list;

	assert(IS_SGI(sgi_id));
	assert(core_pos < PLATFORM_CORE_COUNT);

	assert(mpidr_list[core_pos] != UINT64_MAX);

	/* Extract the affinity information */
	aff0 = MPIDR_AFF_ID(mpidr_list[core_pos], 0);
	aff1 = MPIDR_AFF_ID(mpidr_list[core_pos], 1);
	aff2 = MPIDR_AFF_ID(mpidr_list[core_pos], 2);
#ifndef AARCH32
	unsigned long long aff3;
	aff3 = MPIDR_AFF_ID(mpidr_list[core_pos], 3);
#endif

	/* Construct the SGI target list using Affinity 0 */
	assert(aff0 < SGI_TARGET_MAX_AFF0);
	target_list = 1 << aff0;

	/* Construct the SGI target affinity */
	sgir =
#ifndef AARCH32
		((aff3 & SGI1R_AFF_MASK) << SGI1R_AFF3_SHIFT) |
#endif
		((aff2 & SGI1R_AFF_MASK) << SGI1R_AFF2_SHIFT) |
		((aff1 & SGI1R_AFF_MASK) << SGI1R_AFF1_SHIFT) |
		((target_list & SGI1R_TARGET_LIST_MASK)
				<< SGI1R_TARGET_LIST_SHIFT);

	/* Combine SGI target affinity with the SGI ID */
	sgir |= ((sgi_id & SGI1R_INTID_MASK) << SGI1R_INTID_SHIFT);
#ifndef AARCH32
	write_icc_sgi1r(sgir);
#else
	write64_icc_sgi1r(sgir);
#endif
	isb();
}

void gicv3_set_intr_route(unsigned int interrupt_id,
		unsigned int core_pos)
{
	unsigned long long route_affinity;

	assert(gicd_base_addr);
	assert(core_pos < PLATFORM_CORE_COUNT);
	assert(mpidr_list[core_pos] != UINT64_MAX);

	/* Routing information can be set only for SPIs */
	assert(IS_SPI(interrupt_id));
	route_affinity = mpidr_list[core_pos];

	gicd_write_irouter(gicd_base_addr, interrupt_id, route_affinity);
}

unsigned int gicv3_get_isenabler(unsigned int interrupt_id)
{
	unsigned int core_pos;

	assert(gicd_base_addr);
	assert(IS_VALID_INTR_ID(interrupt_id));

	if (interrupt_id < MIN_SPI_ID) {
		core_pos = platform_get_core_pos(read_mpidr_el1());
		assert(rdist_pcpu_base[core_pos]);
		return gicr_get_isenabler0(rdist_pcpu_base[core_pos], interrupt_id);
	} else
		return gicd_get_isenabler(gicd_base_addr, interrupt_id);
}

void gicv3_set_isenabler(unsigned int interrupt_id)
{
	unsigned int core_pos;

	assert(gicd_base_addr);
	assert(IS_VALID_INTR_ID(interrupt_id));

	if (interrupt_id < MIN_SPI_ID) {
		core_pos = platform_get_core_pos(read_mpidr_el1());
		assert(rdist_pcpu_base[core_pos]);
		gicr_set_isenabler0(rdist_pcpu_base[core_pos], interrupt_id);
	} else
		gicd_set_isenabler(gicd_base_addr, interrupt_id);
}

void gicv3_set_icenabler(unsigned int interrupt_id)
{
	unsigned int core_pos;

	assert(gicd_base_addr);
	assert(IS_VALID_INTR_ID(interrupt_id));

	if (interrupt_id < MIN_SPI_ID) {
		core_pos = platform_get_core_pos(read_mpidr_el1());
		assert(rdist_pcpu_base[core_pos]);
		gicr_set_icenabler0(rdist_pcpu_base[core_pos], interrupt_id);
	} else
		gicd_set_icenabler(gicd_base_addr, interrupt_id);
}

unsigned int gicv3_get_ispendr(unsigned int interrupt_id)
{
	unsigned int ispendr;
	unsigned int bit_pos, core_pos;

	assert(gicd_base_addr);
	assert(IS_VALID_INTR_ID(interrupt_id));

	if (interrupt_id < MIN_SPI_ID) {
		core_pos = platform_get_core_pos(read_mpidr_el1());
		assert(rdist_pcpu_base[core_pos]);
		ispendr = gicr_read_ispendr0(rdist_pcpu_base[core_pos]);
	} else
		ispendr = gicd_read_ispendr(gicd_base_addr, interrupt_id);

	bit_pos = interrupt_id % (1 << ISPENDR_SHIFT);
	return !!(ispendr & (1 << bit_pos));
}

void gicv3_set_icpendr(unsigned int interrupt_id)
{
	unsigned int core_pos;

	assert(gicd_base_addr);
	assert(IS_SPI(interrupt_id) || IS_PPI(interrupt_id));

	if (interrupt_id < MIN_SPI_ID) {
		core_pos = platform_get_core_pos(read_mpidr_el1());
		assert(rdist_pcpu_base[core_pos]);
		gicr_set_icpendr0(rdist_pcpu_base[core_pos], interrupt_id);

	} else
		gicd_set_icpendr(gicd_base_addr, interrupt_id);
}

void gicv3_probe_redistif_addr(void)
{
	unsigned long long typer_val;
	uintptr_t rdistif_base;
	unsigned long long affinity;
	unsigned int core_pos = platform_get_core_pos(read_mpidr_el1());

	assert(gicr_base_addr);

	/*
	 * Return if the re-distributor base address is already populated
	 * for this core.
	 */
	if (rdist_pcpu_base[core_pos])
		return;

	/* Iterate over the GICR frames and find the matching frame*/
	rdistif_base = gicr_base_addr;
	affinity = gic_typer_affinity_from_mpidr(read_mpidr_el1() & MPIDR_AFFINITY_MASK);
	do {
		typer_val = gicr_read_typer(rdistif_base);
		if (affinity == ((typer_val >> TYPER_AFF_VAL_SHIFT) & TYPER_AFF_VAL_MASK)) {
			rdist_pcpu_base[core_pos] = rdistif_base;
			mpidr_list[core_pos] = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
			return;
		}
		rdistif_base += (1 << GICR_PCPUBASE_SHIFT);
	} while (!(typer_val & TYPER_LAST_BIT));

	ERROR("Re-distributor address not found for core %d\n", core_pos);
	panic();
}

void gicv3_setup_distif(void)
{
	unsigned int gicd_ctlr;

	assert(gicd_base_addr);

	/* Check for system register support */
#ifndef AARCH32
	assert(read_id_aa64pfr0_el1() &
			(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT));
#else
	assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT));
#endif

	/* Assert that system register access is enabled */
	assert(is_sre_enabled());

	/* Enable the forwarding of interrupts to CPU interface */
	gicd_ctlr = gicd_read_ctlr(gicd_base_addr);

	/* Assert ARE_NS bit in GICD */
	assert(gicd_ctlr & (GICD_CTLR_ARE_NS_MASK << GICD_CTLR_ARE_NS_SHIFT));

	gicd_ctlr |= GICD_CTLR_ENABLE_GRP1A;
	gicd_write_ctlr(gicd_base_addr, gicd_ctlr);
}

void gicv3_init(uintptr_t gicr_base, uintptr_t gicd_base)
{
	assert(gicr_base);
	assert(gicd_base);

	gicr_base_addr = gicr_base;
	gicd_base_addr = gicd_base;
}