aboutsummaryrefslogtreecommitdiff
path: root/drivers/arm/gic/gic_common.c
blob: 7e76a20edc688887557fccc1ba1d47375bf72350 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
/*
 * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gic_v3.h>
#include <mmio.h>

/*******************************************************************************
 * GIC Distributor interface accessors for reading entire registers
 ******************************************************************************/

unsigned int gicd_read_isenabler(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> ISENABLER_SHIFT;
	return mmio_read_32(base + GICD_ISENABLER + (n << 2));
}

unsigned int gicd_read_icenabler(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> ICENABLER_SHIFT;
	return mmio_read_32(base + GICD_ICENABLER + (n << 2));
}

unsigned int gicd_read_ispendr(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> ISPENDR_SHIFT;
	return mmio_read_32(base + GICD_ISPENDR + (n << 2));
}

unsigned int gicd_read_icpendr(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> ICPENDR_SHIFT;
	return mmio_read_32(base + GICD_ICPENDR + (n << 2));
}

unsigned int gicd_read_isactiver(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> ISACTIVER_SHIFT;
	return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
}

unsigned int gicd_read_icactiver(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> ICACTIVER_SHIFT;
	return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
}

unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> IPRIORITYR_SHIFT;
	return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
}

unsigned int gicd_read_icfgr(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int n = interrupt_id >> ICFGR_SHIFT;
	return mmio_read_32(base + GICD_ICFGR + (n << 2));
}

/*******************************************************************************
 * GIC Distributor interface accessors for writing entire registers
 ******************************************************************************/

void gicd_write_isenabler(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> ISENABLER_SHIFT;
	mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
}

void gicd_write_icenabler(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> ICENABLER_SHIFT;
	mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
}

void gicd_write_ispendr(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> ISPENDR_SHIFT;
	mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
}

void gicd_write_icpendr(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> ICPENDR_SHIFT;
	mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
}

void gicd_write_isactiver(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> ISACTIVER_SHIFT;
	mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
}

void gicd_write_icactiver(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> ICACTIVER_SHIFT;
	mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
}

void gicd_write_ipriorityr(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> IPRIORITYR_SHIFT;
	mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
}

void gicd_write_icfgr(uintptr_t base,
				unsigned int interrupt_id, unsigned int val)
{
	unsigned int n = interrupt_id >> ICFGR_SHIFT;
	mmio_write_32(base + GICD_ICFGR + (n << 2), val);
}

/*******************************************************************************
 * GIC Distributor interface accessors for individual interrupt manipulation
 ******************************************************************************/
unsigned int gicd_get_isenabler(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1);

	return gicd_read_isenabler(base, interrupt_id) & (1 << bit_num);
}

void gicd_set_isenabler(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int bit_num = interrupt_id & ((1 << ISENABLER_SHIFT) - 1);

	gicd_write_isenabler(base, interrupt_id, (1 << bit_num));
}

void gicd_set_icenabler(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int bit_num = interrupt_id & ((1 << ICENABLER_SHIFT) - 1);

	gicd_write_icenabler(base, interrupt_id, (1 << bit_num));
}

void gicd_set_ispendr(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int bit_num = interrupt_id & ((1 << ISPENDR_SHIFT) - 1);

	gicd_write_ispendr(base, interrupt_id, (1 << bit_num));
}

void gicd_set_icpendr(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int bit_num = interrupt_id & ((1 << ICPENDR_SHIFT) - 1);

	gicd_write_icpendr(base, interrupt_id, (1 << bit_num));
}

void gicd_set_isactiver(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int bit_num = interrupt_id & ((1 << ISACTIVER_SHIFT) - 1);

	gicd_write_isactiver(base, interrupt_id, (1 << bit_num));
}

void gicd_set_icactiver(uintptr_t base, unsigned int interrupt_id)
{
	unsigned int bit_num = interrupt_id & ((1 << ICACTIVER_SHIFT) - 1);

	gicd_write_icactiver(base, interrupt_id, (1 << bit_num));
}

unsigned int gicd_get_ipriorityr(uintptr_t base, unsigned int interrupt_id)
{
	return gicd_read_ipriorityr(base, interrupt_id) & GIC_PRI_MASK;
}

void gicd_set_ipriorityr(uintptr_t base, unsigned int interrupt_id,
				unsigned int priority)
{
	mmio_write_8(base + GICD_IPRIORITYR + interrupt_id,
			priority & GIC_PRI_MASK);
}

unsigned int is_gicv3_mode(void)
{
	/* Check if GICv3 system register available */
#ifdef __aarch64__
	if (!(read_id_aa64pfr0_el1() & (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)))
		return 0;
#else
	if (!(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)))
		return 0;
#endif

	/* Check whether the system register interface is enabled */
	return !!is_sre_enabled();
}