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2020-10-28Tegra194: Add platform tag to serror_sdei_event_handleranzhou
The function serror_sdei_event_handler has been defined in inject_serror.S, Tegra194 has different function content with the common function. Rename it to tegra194_serror_sdei_event_handler. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I5a619abcf6aca5215da38f3a74fc229f5b2ec770
2020-10-27cactus: macros for processing of commandsJ-Alves
Set of macros to be used for sending and handling commands to and from cactus. The implemented macros use ffa direct messaging interfaces. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I4e02933167ce078d3a467881eece588fa460510b
2020-10-27SPM: memory sharing functions and structuresJ-Alves
Added structures and functions for memory sharing operations: Structures are defined according to the FFA specification; the functions encompass structures initialization helpers. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Ic4e6adbf4e7085a2d62373ed823934c42f539d12
2020-10-27FFA: Mem sharing ABIsJ-Alves
Implementation of wrappers for FFA ABI calls: - FFA_MEM_DONATE; - FFA_MEM_LEND; - FFA_MEM_SHARE; - FFA_MEM_RETRIEVE_REQ; - FFA_MEM_RELINQUISH; - FFA_MEM_RECLAIM. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I44853190d11689501a84bf3624b9b0bf6cfb06a7
2020-10-23Tegra194: support GET_SMMU_PER testinganzhou
This patch introduces a test to get return value from SMC SiP function TEGRA_SIP_GET_SMMU_PER. This is a common function for all Tegra platforms. This patch enables the test for Tegra194 platforms. Signed-off-by: anzhou <anzhou@nvidia.com> Change-Id: I14d82aecdbccc02ce3965b52230500bf487a0cc3
2020-10-23Tegra194: introduce tests to verify the Video Memory resize interfaceVarun Wadekar
Tegra platforms provide support to program the Video memory aperture and increase or decrease the size at run time. This test verifies the interface for the following positive and negative scenarios: * verify that incorrect input parameters are handled properly * verify that the memory region is programmed and can be resized later * verify that no information is leaked after the resize operation Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Id554b2c565a85a62ba4524b2faf7d41d3d506f18
2020-10-23timers: remove dependency on SYS_CNT_BASE1Varun Wadekar
The Arm ARM Section D11.1.1 titled "The full set of Generic Timer components" says that Memory-mapped timers are optional. The timer framework and tests use the SYS_CNT_BASE1 macro to read the memory mapped timers. But they can also read the CNTPCT_EL0 system register to get the same value to accommodate all Arm platforms. This patch replaces the usage of SYS_CNT_BASE1 from the timer code with calls to syscounter_read(). Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I4d9ee5587351ee737800539f4d48606e7de80538
2020-10-19SMC fuzzing module integration.Mark Dykes
This includes one test with one seed as the initial implementation. A future upgrade will include an enhanced seeding strategy. The patch includes an example device tree file with the actual test (sdei.dts) leveraging the SDEI functions that can be called without reference to system state. Platform CI will have a single TFTF config to be used in all future testing. Once both branches of TFA tests and platform CI are checked in a user can invoke the testing with: workspace=<workspace location> test_groups=fvp-aarch64-sdei,fvp-smcfuzzing:fvp-tftf-fip.tftf-aemv8a test_run=1 bin_mode=debug retain_paths=1 ./platform-ci/script/run_local_ci.sh Signed-off-by: Mark Dykes <mark.dykes@arm.com> Change-Id: Ic290e7255bcfd845c0d22037e0b670a6691541df
2020-10-14Merge "Remove dependencies from FVP to generic code"Madhukar Pappireddy
2020-10-09Remove dependencies from FVP to generic codeJavier Almansa Sobrino
Some generic parts of TFTF have dependencies from FVP platform macros which can cause some trouble when porting the tests to a different platform. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I11eb1af142b8c0ee1de2fcc8f298658bceedf306
2020-10-07Add test for SDEI RM_ANY routing modejohpow01
Previously, there were no tests using the RM_ANY routing mode. That particular flag doesn't affect code flow very much, it's mainly used for GIC configuration of the interrupt, so this is a test of basic functionality. This test case makes sure RM_ANY event registrtation works and that events can be routed to all CPUs. It does this by registering an SDEI event with the RM_ANY flag, powering up all CPUs, then generating events. Each time a CPU receives an event it shuts off and the process repeats. Every CPU must receive a single event or the test will not pass. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I1ebd0565158d93bddbf58d680d4696086ac00234
2020-09-17cactus: re-align secure partition idOlivier Deprez
According to [1] and [2] secure partition ids are defined from 0x8001 to 0xfffe. Update the cactus test payload and TFTF such that it uses the appropriate IDs. 0x8000 and 0xffff are reserved FF-A IDs respectively for the SPMC and the SPMD. Conversely in the NWd, the Hypervisor ID is 0 and VMs are numbered in the range of 1 to 0x7fff. [1] https://trustedfirmware-a.readthedocs.io/en/latest/components/ secure-partition-manager.html#ffa-id-get [2] https://review.trustedfirmware.org/c/hafnium/hafnium/+/5165 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3e9786212b227e6637a7650e60ddc4e59ad05a46
2020-09-02Minor bug fixes in multicore IRQ spurious testMadhukar Pappireddy
Program the memory mapped GIC_ITARGETSR register with appropriate cpu mask and assert the expected value is returned upon reading the register. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I356111d763569c229d7f4c9ea3cd4899305a4954
2020-08-19Cactus: Map RXTX region to third partion.Ruari Phipps
When the third cactus partition is booted, map the RXTX region using the FFA_RXTX_MAP ABI. If this is successful, point the mailbox to this RXTX region. Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Change-Id: Ifbe3bc70b187f75f29ef66356e714e8a905d2db8
2020-08-17Tegra194: support for RAS corrected error testingVarun Wadekar
This patch introduces a test to inject RAS corrected errors for all supported nodes from all CPUs. On injecting an error, the CPU verifies that the error was detected with the help of an IRQ. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I4a679e432d36e20aac64e7062fbaab438e96dfc0
2020-08-17Tegra194: introduce RAS uncorrectable error injection testsVarun Wadekar
Platform vendors have some tests that are specific to their platforms. This patch introduces a test suite for Tegra194 platfoms. As the first test, the platform will inject the RAS uncorrectable errors and verify that the platform detects and reports them. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Id7b26d35dd4c638c2bd92959f18f12423ec1fd8b
2020-07-28Update SMCCC_ARCH_SOC_ID test caseManish V Badarkhe
Skip the test result if SMCCC_ARCH_SOC_ID feature is not available for the platform and also, return failure in case of SMCCC_ARCH_SOC_ID feature is available but platform unable to provide either soc-revision or soc-version information. Change-Id: I447adb78814a902a4344d98e4f7fafe67000316f Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2020-07-27Cactus: FFA_PARTITION_INFO_GET test.Max Shvetsov
Calls FFA_PARTITION_INFO_GET API from secure virtual FFA-A instance. * Gets information about primary SP. * Gets information about secondary SP. * Gets information about all SP running. * Attempts to get information about non-existing SP. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Ief4de45b4d7decb1e1dba9bdb0e7e05516062dd2
2020-07-27Cactus: FFA_FEATURES test.Max Shvetsov
Calls FFA_FEATURES API from the secure virtual FF-A instance which is serviced by SPMC. Expected responses should be edited according to the feature implementation progress. Removing obsolete SPRT version check and cactus_tests_misc.c as a result. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I8a2e569a3bce31a735e1af04994984fda2168296
2020-07-27SPM: TFTF test of FFA_FEATURES interface.Max Shvetsov
Forwards FFA_FEATURES call to SPMC via SPMD from the normal world. Expected responses should be edited according to the feature implementation progress. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I057100b4086108b0779e3fa76fbd86e0818f765c
2020-07-17Merge "remove dashes and and sort tests"joanna.farley
2020-07-14remove dashes and and sort testsLeonardo Sandoval
remove dashes on 'make help_tests' output aligns a bit more to main 'make help' output. Also, sort tests sets so users find quicker the name of the test. Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: If09992ddff95865233b1a311f9a52600d3756556
2020-06-30TFTF doesn't need to boot Secondary CactusJ-Alves
Removed code that was booting Cactus Secondary, using FFA_RUN interface from TFTF's SPM tests. Hafnium now boots all partitions according to "boot-order" field value in the partition manifests. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I31a3507c92bffe81f78036da121259a5c19924cd
2020-06-26Tidying FFA helpersJ-Alves
Moved SP specific functions/macros to "sp_helpers.c/h". Placed ffa interfaces/symbols shared between tftf and SPs in "ffa_helpers.c/h". Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I4cf967f87837ce3e7d0f7244f9cc0677f608f9cd
2020-06-19SPM: TFTF test of FFA_VERSION interfaceJ-Alves
Implemented test to FFA_VERSION interface: - "test_ffa_version.c" contains functions to test FFA_VERSION ABI; - Test suite for FFA_VERSION ABI in tests-spm.xml; - Helper macros changed in "ffa_helpers.h". Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I6b0e937e30fceaa21a57c4ba0761a62049b16c0d
2020-06-08tests: arm_arch_svc: introduce support for NVIDIA Denver CPUsVarun Wadekar
This patch introduces support for NVIDIA Denver CPUs and variants in the SMCCC_ARCH_WORKAROUND_1 test. Verified with TFTF ARM_ARCH_SVC test on Tegra194. <snip> Running test suite 'ARM_ARCH_SVC' Description: Arm Architecture Service tests > Executing 'SMCCC_ARCH_WORKAROUND_1 test' INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off TEST COMPLETE Passed <snip> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibe179b43fd6a43c4fb5c6cdc7b0c78904efb1b5e
2020-06-03Merge changes from topic "jb/8.6-features"Manish Pandey
* changes: Test that TF-A supports ARMv8.6-ECV Test that TF-A supports ARMv8.6-FGT
2020-06-03Test that TF-A supports ARMv8.6-ECVJimmy Brisson
Note: This test will cause an unhandled exception in the case that TF-A is not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware supports it. Change-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-05-29Test that TF-A supports ARMv8.6-FGTJimmy Brisson
Note: This test will cause an unhandled exception in the case that TF-A is not doing its job and enabling ARMv8.6-FGT when the hardware supports it. Change-Id: Iae0fe39895909248b5e7b07a1a73f7702adce7dd Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-05-28Bug fix in Multicore IRQ spurious test.Madhukar Pappireddy
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: Iaf160c8bc9c5807fc9263f5250c0aeedc20e5a8a
2020-05-15SPCI is now called PSA FF-AJ-Alves
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA FF-A(in documents) or simply FFA(in code). Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I17728c1503312845944a5ba060c252c2b98f3e91
2020-04-29Add test case for SMCCC_ARCH_SOC_ID featureManish V Badarkhe
Added test case for "SMCCC_ARCH_SOC_ID" SMC call. This SMC call is used to retrieve SOC version and SOC revision Test execution output is as below: > Executing 'SMCCC_ARCH_SOC_ID test' TEST COMPLETE Passed SOC Rev is not implemented SOC Ver = 0x43b0000 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I48668ce22bb5d5767dadb42ce9526d77fd916bed
2020-03-26tftf: spci: probe if SPMC is OP-TEE at S-EL1Olivier Deprez
For pre-Armv8.4 platform, the supported model is that SPMC runs at S-EL1. The candidate is OP-TEE with SPCI protocol adaptation. This patch performs a version check through direct messaging and determines if OP-TEE runs as SPMC by checking version responses. If this does not match, then it assumes SPMC runs at S-EL2 with two Cactus instances running at S-EL1. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I34194b6e8b3d447a25f2153bbac1be2631cd7a5e
2020-03-23tftf: re-introduce spm tests in the flowOlivier Deprez
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3a80e023c71426605abb13303d466a9b93f3123e
2020-03-20tftf: SPCI Beta1 add direct messaging testOlivier Deprez
This patch strips out former SPCI Alpha sample test code. Removing SPRT references will be done in another coming patch. Version check is adapted to SPCI Beta1. Version is now returned in x2. The first test is a direct messaging test using SPCI_MSG_SEND_DIRECT_REQ targetting a bare-metal cactus SP. TFTF expects a response from the SP returning with SPCI_MSG_SEND_DIRECT_RESP. Note: this patch also provides an initial SPCI_RUN interface. This API may not be used in the mid-term because VM to SP communication is supposed to be done only through direct messaging. Though the SPM boot-up for now is only launching the first SP in the list of declared SP in SPMC manifest. In order to make 2nd-VM ready, TFTF has to "boot-up" the SP through a single SPCI_RUN invocation till it reaches SPCI_MSG_WAIT in the SP. Once SPM implements boot up through all SPs, this SPCI_RUN invocation will no longer be required. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I141abd3e348409b3d34a911d0552570f49e85846
2020-02-11Switch AARCH32/AARCH64 to __aarch64__Deepika Bhavnani
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) NOTE: This change is based on below TFA commit https://github.com/ARM-software/arm-trusted-firmware/commit/402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: If2c3dbaeb01d4a9d8cfd95d906e5eaf4ae94417f
2020-01-30TF-TF: Store boot parametersAlexei Fedorov
This patch adds support for storing fw_config and hw_config addresses passed as arg0 and arg1 parameters in x0, x1 from BL31. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I58ae379bb4a7ef1b6ce60a4e252c65d34dc14464
2020-01-13Make TFTF RFC 4122 compliantOliver Swede
This is a TFTF backport of a change that makes TF RFC 4122-compliant by converting the stored format of UUIDs from machine order (little endian) to network order (big endian). This patch changes the data structure used to store the values in the same way as in the related change in TF: 033648652f2d66abe2454a75ded891a47cb13446. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I052e570b80de61f87a049a08e347a2e5da7f841b
2019-12-23debugfs: add debug filesystem testsAmbroise Vincent
Change-Id: Idc36627dabe5af0076fe300ee0c071dce1662a0d Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
2019-12-12TFTF: Add missing D-cache invalidationAlexei Fedorov
This patch adds missing D-cache invalidation of RW memory in tftf_entrypoint to safeguard against possible corruption of this memory by dirty cache lines in a system cache as a result of use by an earlier boot loader stage. Ref. GENFW-3455 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I595344c307502a6c24c2e62d3e3f2f9d7a810dfa
2019-12-05Merge "Support for extended register usage in SMCCC v1.2 spec"Manish Pandey
2019-11-29Merge "TFTF: Add support for FVP platforms with SMT capabilities"Soby Mathew
2019-11-21Support for extended register usage in SMCCC v1.2 specMadhukar Pappireddy
The new version of SMC Calling Convention spec makes X0-X7/W0-W7/R0-R7 registers available for returning results and X1-X7/W1-W7/R1-R7 for passing arguments during SMC calls. This patch makes necessary changes to support the update in register usage and also enhances existing test case to check for expected behavior across SMC call. Link to the SMCCC spec: https://developer.arm.com/docs/den0028/c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I9e5a3e4f9de388cb9a7426b0eae1c0fa1229292a
2019-11-13Merge "`requested_irq_received` must be initialized for all tests"Sandrine Bailleux
2019-11-07TFTF: Add support for FVP platforms with SMT capabilitiesAlexei Fedorov
This patch adds support for Simultaneously MultiThreaded (SMT) cores on FVP models. Number of threads per CPU is passed in FVP_MAX_PE_PER_CPU build parameter which can be set either to 1 or 2. This option defaults to 1. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: Ib0e2afe429e8f24b8a74ad6ee98750ed1ac121fb
2019-10-30Aarch32: Secure PMU counter leak testsPetre-Ionut Tudor
This patch adds Aarch32 support to the PMU counter leak tests. These tests attempt to profile the Secure world by configuring EL0 system registers such that the PMU is told to increment counters at Secure EL1, Secure EL2 and EL3. The tests fail if useful information was leaked. The Secure world defends against this type of attack with a combination of configuring EL3 system registers and saving/restoring EL0 PMU registers. Exactly which defense is employed depends on the architecture version. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a
2019-10-21Merge "Extend SYSTEM_OFF test case"v2.2-rc2Sandrine Bailleux
2019-10-18Extend SYSTEM_OFF test caseDeepika Bhavnani
Extend SYSTEM_OFF to involve more than just the lead CPU. The typical way to use SYSTEM_OFF is to use calls to CPU_OFF on all online cores except for the last one, which instead uses SYSTEM_OFF. test_system_off_cpu_other_than_lead() case is added to turn on any random CPU other then lead CPU and perform SYSTEM_OFF from the CPU which was turned ON. Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ice62d0e7ef0db63ccb030e8dc1a83d9bd55e70f2
2019-10-14`requested_irq_received` must be initialized for all testsDeepika Bhavnani
requested_irq_received is used to confirm if the CPU is woken by IRQ, it is set as part of `requested_irq_handler`. Default it should be cleared for all CPU's under test, un-intialized value resulted in random failure based on previous state of variable. Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ia3af99a11f3297c2e8fc1ef52e7f18107e2fdfc8
2019-10-10Bugfix for PMU leakage testPetre-Ionut Tudor
This patch fixes a bug where integer underflow causes the tests to wrongly fail. Since event counts are register values, they are unsigned in TFTF. When the event count is less on the SMC being profiled than the baseline SMC event count, subtraction causes an underflow which goes beyond the allowed deviation and makes the test fail. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I58bc18ca4afd28b6d1b1354a9af9f70d616d2c32