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Some platform specific defines found in 'fwu_nvm.h' header
hence moved such define to platform specific header file.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I1cfd1c95306e2ded5b78d1d6424ad159a958c502
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This test was disabled here:
https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/3672
This was due to an outdated SCP firmware version causing it to fail. The
SCP binaries have been updated and this test no longer fails, so it can
be safely reenabled.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieb647a1416eb99832a560c54c9e8f7d8fbbbc707
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This patch fixes the bug in tftf_plat_configure_mmu()
function (tf-a-tests\plat\common\plat_common.c) which
is missing setting MT_NS attribute flag when maps
Code, RO data and RW Data + BSS memory regions, causing
them to be reported as Secure memory:
[LV3] VA:0x88000000 PA:0x88000000 size:0x1000 MEM-RO-EXEC-S
...
[LV3] VA:0x88016000 PA:0x88016000 size:0x1000 MEM-RO-XN-S
...
[LV3] VA:0x88020000 PA:0x88020000 size:0x1000 MEM-RW-XN-S
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: If64aa65179ffe223d3e6f1c6bf73a7e4ce7fa536
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This patch uses PPI 26 as the per-CPU Hypervisor Timer Interrupt ID.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3e70aec91c129f57b39ca0d1165148880d59c8b3
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CPUs on Tegra194 platforms cannot be woken up with the RTC timer interrupt after
power off.
This patch skips the following tests as a result:
* Timer framework Validation/Target timer to a power down cpu
* Timer framework Validation/Test scenario where multiple CPUs call same timeout
* Timer framework Validation/Stress test the timer framework
These tests can be enabled once we figure out the right timer source to use for
CPU wakeup.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I0f8154e285391fc35fe33428051ab1036ca9c845
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This patch adds support for WDT0 that is connected to CPU0 to act as the
watchdog timer for Tegra194 platforms. The watchdog timer uses TMR0 as the
source and fires if the CPU is hung for more than 10 seconds.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibe20c1130f86718b919c89436d7f5f49b74d9cc9
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The RTC consumes 250us for each register read/write. Increase the step
value to 5ms to cover all the register read/write in program_timer().
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Iac0fc070dbf85a6352fbf147fc5945820e8ee495
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This patch creates a dummy SMMU context and saves the base address
to a pre-negotiated scratch register for the System Resume Firmware
to restore. This allows the System Resume Firmware to complete
without any errors or warnings.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic596e6775c6b78ac051ccff02e9574186d6f5335
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This patch introduces the flexibility to reset the platform via
the SMC_PSCI_SYSTEM_RESET function ID.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I315315f1998d9b9d8f237ac05625328175880922
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This patch disables the following test cases from the PSCI System
Suspend Validation test suite:
* system suspend from all cores
* Suspend system with cores in suspend
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I5f6fcf01ad3b9012fac684f9b3beb87827148de0
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Tegra194 platforms do not support CPU suspend power down and cannot
be woken up with an SGI. This patch disables the following tests as
a result.
+ PSCI Affinity Info/Affinity info level0 powerdown
+ PSCI CPU Suspend/CPU suspend to standby at level 0
+ PSCI CPU Suspend/CPU suspend to standby at level 1
+ PSCI CPU Suspend/CPU suspend to standby at level 2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I082f254fcd07f9b504f366f2f9a4b41cf7d6bbc3
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This patch introduces support for adding RTC as a wake source to
exit System Suspend state.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib08d6e2ee7944cd46a91d272ceebffc67b8d7c66
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This patch introduces support to enter the System Suspend power state. The
required context is saved to allow the platform to enter and resume from
the state.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Iaeaf065f87a2b20981aa92a14fa964802fada20c
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This patch contains the basic platform support for Tegra194 platforms
to initialize the tftf framework and execute tests on the CPUs.
The tests require support for a timer, non-volatile memory, UART and
GIC. This port uses Tegra_TMR0 as the timer, TI UART 16550 as the
console and DRAM as NVM. The GIC driver provided by ARM is used as is.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2da2121cb05445f47b7d3083cdd6ac6d52586797
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This patch extends passing FVP topology parameters with
FVP_CLUSTER_COUNT and FVP_MAX_CPUS_PER_CLUSTER build
options to match TF-A. The change adds more test options,
make FVP platform configuration more flexible and eliminates
test errors when the platform is configured with number
of CPUs less than default values in the makefile.
These build options are documented in 'Arm FVP Platform
Specific Build Options' section of 'build-options.rst'
document.
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I01c6437d468885755a5415804b3688e4c878170d
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Till now only pl011 UART is available stdout but there is a usecase to
redirect it to other channel.
This patch decouples console_putc implementation from pl011.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I38e8c5c90421fad2425228f407e6f29bdf6b08c7
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The issue with the test has been fixed with the TF-A patch:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3778
so re-enable it.
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: Ie394b596c7da504c74c684af3ef5f6065a05eef9
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This test fails on sgi575 models 11.9 release, the reason for failure
is old SCP firmware version which is 2.3.
With SCP version 2.5 above this issues does not occurs.
This patch can be reverted once the SCP FW binary updated on CI.
Change-Id: I453f3ef3e22272e0b2c61c96c98f1710eec8d1ca
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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The issue with this test is fixed with the
TF-A patch: https://review.trustedfirmware.org/c/TF-A/
trusted-firmware-a/+/3591, so re-enable it.
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: I343a017eea8a134ce74dedd484faaafdeb65ef13
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This test often fails on FVP_Base_Cortex-A55x4+Cortex-A76x2. This is under
investigation. This patch disables the test in the meantime.
Change-Id: I09e5c67ccce51b8dc9843dacb3375b17679df9a8
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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* changes:
Max SPI INTID is 1019
Switch AARCH32/AARCH64 to __aarch64__
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Elements in fvp_power_domain_tree_desc and PLATFORM_CORE_COUNT are
multiplied by FVP_MAX_PE_PER_CPU in order to implement the correct
topology.
Change-Id: Icb979d719a1b4aac39a95b2829fcabaa53bdedaf
Signed-off-by: Imre Kis <imre.kis@arm.com>
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The NODE_HW_STATE tests seem to hang on Juno. This needs to be investigated.
Disable them in the meantime.
Change-Id: I355aa8fea839f2054340f9e7a8a6fdc2f526e63d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)
NOTE: This change is based on below TFA commit
https://github.com/ARM-software/arm-trusted-firmware/commit/402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: If2c3dbaeb01d4a9d8cfd95d906e5eaf4ae94417f
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The model has been updated to a newer version which fixed the
issues causing the PMU tests to fail, so they are being re-enabled
on this platform.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ie2c7a610432a13edb05630d319cd0e8d7148b834
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The PMU tests currently fail on SGI-575 platform. The root cause is unknown at
this point and some further investigation is needed.
Skip these tests in the meantime.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ia43d1ccef8394e2ac8f08c28f32aa68cf045781a
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This patch adds support for Simultaneously MultiThreaded (SMT)
cores on FVP models. Number of threads per CPU is passed in
FVP_MAX_PE_PER_CPU build parameter which can be set either to
1 or 2. This option defaults to 1.
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: Ib0e2afe429e8f24b8a74ad6ee98750ed1ac121fb
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This patch provides the following feature and makes
modification listed below:
- ARMv8.3-PAuth tests now check for all keys being in use
(e.g. APIAKey when the test suite is built with
`ENABLE_PAUTH=1` option) and program new key values otherwise.
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifa4a288274822029da585073563c68a1434f5de7
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This patch provides the following features and makes
modifications listed below:
- `plat_init_apiakey()` function is replaced with `init_apkey()`
which returns 128-bit value and uses Generic timer physical counter
value to increase the randomness of the generated key.
The new function can be used for generation of all ARMv8.3-PAuth keys.
- Source file `pauth.c` moved from `plat/common/aarch64`
to `lib/extensions/pauth/aarch64` folder which contains PAuth specific
code.
- Individual APIAKey key generation for each CPU on every warm boot.
- Per-CPU storage of APIAKey added in `tftf_suspend_context` structure.
- APIAKey key is saved/restored in arch context on entry/exit from
suspended state.
- Added `pauth_init_enable()` function which generates, programs
and enables APIAKey in EL1/EL2.
- Changes in documentation related to ARMv8.3-PAuth support.
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I964b8f964bb541cbb0b2f772cb0b07aed055fe36
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This prevents the execution of the read-only data.
This is done in a similar way in TF-A when the build flag
SEPARATE_CODE_AND_RODATA is enabled.
The build flag is probably not needed in TF-A Tests.
Change-Id: I2bdc0237c00377beb2febeb47207770c85036192
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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This patch fixes the bug in tftf_get_total_aff_count()
which incorrectly calculates the number of CPUs for
aff_lvl = 0. The function reads tftf_pd_nodes[] array
only based on condition
`tftf_pd_nodes[node_idx].level == aff_lvl` but
doesn't check for `indexes < PLATFORM_NUM_AFFS`.
This causes reads of the array beyond its boundaries
which results in incorrect calculation of number of CPUs,
and some of the tests entering infinite loops.
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: If7b2d8eba7560126aeff29c6b8c9355198aad453
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This specific test is known to have unstable behaviour. As a temporary
solution we skip this test for AArch64 Juno configs.
Change-Id: I7c93de0c80ad8dba47b83f0b343d868dc18b732f
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Few Cortex FVPs have upto 8 CPUs in single clsuter. This patch solves
the issue reported in https://developer.trustedfirmware.org/T333
Change-Id: I14c36b0d643a85527b7122cee0f728fddb871ec7
Signed-off-by: Madhukar Pappireddy<madhukar.pappireddy@arm.com>
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It was not possible to get a parent node given an MPIDR
of the CPU using the current topology APIs. This patch adds
the `tftf_get_parent_node_from_mpidr()` API to achieve the same.
Change-Id: I818f1e628689928293c1fdb85606885e851a5785
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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This is needed to have room for xlat v2 tests.
Change-Id: Ic4e39f8f964c2c41effc99f1b419cf7cdc405bbb
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Add basic unit tests for the xlat tables library v2.
Change-Id: I814470d2aceec8a7d1da5190c7c5b355178b1a54
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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* changes:
Add ARMv8.3 pointer authentication support
Remove pointer authentication test
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The code has been taken from commit 99f4fd283b6f ("cactus: Use UART2
instead of UART0") and modified slightly to be integrated in the current
master.
There are three tests that are failing in the CI. They have been
disabled for the time being:
- mem_attr_changes_tests() in cactus_main() in the file
spm/cactus_mm/cactus_mm_main.c.
- Two tests in the file tftf/tests/tests-spm-mm.xml.
Change-Id: I6332cbff1cefeb82b9447fae1b613879e65186a1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.
This feature is supported only in AArch64 state.
This feature is mandatory in ARMv8.3 implementations.
This patch adds the functionality needed for platforms to provide
authentication keys for the TF-A Test Framework, and a new option
(ENABLE_PAUTH) to enable pointer authentication in the framework itself.
This option is disabled by default.
Pointer authentication support has been added to FVP.
Change-Id: Id2d5c978deb68ae60107879f1c3d0b231cba9f42
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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RD-N1-Edge platform consists of two clusters of four CPU's
each. The FVP for this platform does not support system suspend and
resume functionality as there is no wakeup source supported. So all
the system suspend and resume related tests are skipped.
Change-Id: I33649c7c67023127e736c760bf0ec4193c95ed1a
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Change-Id: Iee1998b9b039dfd21a3ef38c5afeae3fc65569c2
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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Enforce full include path for includes.
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them with the same name).
Change-Id: I45e912b16c9fff81f50840dad7e7f90ed6637b2a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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hikey960 has an unresolved power management bug, so for now we can only
run single core tests. The bug report can be found here:
https://bugs.96boards.org/show_bug.cgi?id=783
Change-Id: I206fafd7677428f81f48d1c7c1d419402149bd37
Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com>
Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Change-Id: I728dcf1121317b52418519421cd12929b00dfac0
Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com>
Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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defines and memory mapping for hikey960
Change-Id: I35c57ab0d17553d4f9e1d1b027c4a2308722a870
Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com>
Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Initial commit to allow building hikey960 as a target
Change-Id: Ifaae59b06aaa4065668f05e17eac1a7e2a19ca14
Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com>
Co-authored-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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