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2020-07-27Cactus: tidying FFA_VERSION test.Max Shvetsov
Moving FFA_VERSION test to separate test function. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I09f1ca726eddbcaba0416f981eae292ba88c64b4
2020-07-27Cactus: FFA_PARTITION_INFO_GET test.Max Shvetsov
Calls FFA_PARTITION_INFO_GET API from secure virtual FFA-A instance. * Gets information about primary SP. * Gets information about secondary SP. * Gets information about all SP running. * Attempts to get information about non-existing SP. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Ief4de45b4d7decb1e1dba9bdb0e7e05516062dd2
2020-07-27Cactus: FFA_FEATURES test.Max Shvetsov
Calls FFA_FEATURES API from the secure virtual FF-A instance which is serviced by SPMC. Expected responses should be edited according to the feature implementation progress. Removing obsolete SPRT version check and cactus_tests_misc.c as a result. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I8a2e569a3bce31a735e1af04994984fda2168296
2020-07-27SPM: TFTF test of FFA_FEATURES interface.Max Shvetsov
Forwards FFA_FEATURES call to SPMC via SPMD from the normal world. Expected responses should be edited according to the feature implementation progress. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I057100b4086108b0779e3fa76fbd86e0818f765c
2020-07-21Merge "plat/arm: Move defines to platform specific header file"Madhukar Pappireddy
2020-07-20plat/arm: Move defines to platform specific header fileManish V Badarkhe
Some platform specific defines found in 'fwu_nvm.h' header hence moved such define to platform specific header file. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I1cfd1c95306e2ded5b78d1d6424ad159a958c502
2020-07-17Merge "remove dashes and and sort tests"joanna.farley
2020-07-15Merge "TFTF doesn't need to boot Secondary Cactus"Manish Pandey
2020-07-14remove dashes and and sort testsLeonardo Sandoval
remove dashes on 'make help_tests' output aligns a bit more to main 'make help' output. Also, sort tests sets so users find quicker the name of the test. Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: If09992ddff95865233b1a311f9a52600d3756556
2020-07-08Merge "Add explicit barrier before sev() in tftf_send_event_common API"Sandrine Bailleux
2020-07-04Add explicit barrier before sev() in tftf_send_event_common APIMadhukar Pappireddy
Consider the following scenario: If sev() gets reordered above the event->cnt+=inc operation in tftf_send_event_common() on core 0, and lets say core 1 is in wfe in tftf_wait_for_event, core 1 receives the event before the write to event->cnt from core 0 propagates to core 1. Later, core 1 wakes up, reads event->cnt, sees that it is 0 and goes back to wfe, thereby leading to hang. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I2e8a5ab7c220b02d5b637dc7cdf3562ca73dbfdc
2020-07-02Merge "TFTF: Fix regions' mapping with no NS bit set"Mark Dykes
2020-07-01Merge "include 'path/to' prefix when specifying tftf.bin on make fip cmd"Lauren Wehrmeister
2020-07-01Merge "sgi575: Reenable PSCI NODE_HW_STATE test"Sandrine Bailleux
2020-06-30Merge "TFTF: get FVP platform's topology from build options"Manish Pandey
2020-06-30TFTF doesn't need to boot Secondary CactusJ-Alves
Removed code that was booting Cactus Secondary, using FFA_RUN interface from TFTF's SPM tests. Hafnium now boots all partitions according to "boot-order" field value in the partition manifests. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I31a3507c92bffe81f78036da121259a5c19924cd
2020-06-29include 'path/to' prefix when specifying tftf.bin on make fip cmdLeonardo Sandoval
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: I7c316acd486346332403c758f632147ab71c48f2
2020-06-26sgi575: Reenable PSCI NODE_HW_STATE testjohpow01
This test was disabled here: https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/3672 This was due to an outdated SCP firmware version causing it to fail. The SCP binaries have been updated and this test no longer fails, so it can be safely reenabled. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ieb647a1416eb99832a560c54c9e8f7d8fbbbc707
2020-06-26Merge "Tidying FFA helpers"Manish Pandey
2020-06-26Tidying FFA helpersJ-Alves
Moved SP specific functions/macros to "sp_helpers.c/h". Placed ffa interfaces/symbols shared between tftf and SPs in "ffa_helpers.c/h". Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I4cf967f87837ce3e7d0f7244f9cc0677f608f9cd
2020-06-26Merge "Update FIP corrupt address"Sandrine Bailleux
2020-06-23Merge changes from topic "spm_ffa_version"Manish Pandey
* changes: Cactus: FFA Version Test SPM: TFTF test of FFA_VERSION interface
2020-06-19Cactus: FFA Version TestJ-Alves
Added simple test of the FFA interface to cactus: - FFA version ABI helper; - New test file for test to FFA ABIs; - Invoking "ffa_tests" from cactus main. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I8c8445ad6d9da79f1880d143836e7a6da68eaff7
2020-06-19SPM: TFTF test of FFA_VERSION interfaceJ-Alves
Implemented test to FFA_VERSION interface: - "test_ffa_version.c" contains functions to test FFA_VERSION ABI; - Test suite for FFA_VERSION ABI in tests-spm.xml; - Helper macros changed in "ffa_helpers.h". Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I6b0e937e30fceaa21a57c4ba0761a62049b16c0d
2020-06-17TFTF: Fix regions' mapping with no NS bit setAlexei Fedorov
This patch fixes the bug in tftf_plat_configure_mmu() function (tf-a-tests\plat\common\plat_common.c) which is missing setting MT_NS attribute flag when maps Code, RO data and RW Data + BSS memory regions, causing them to be reported as Secure memory: [LV3] VA:0x88000000 PA:0x88000000 size:0x1000 MEM-RO-EXEC-S ... [LV3] VA:0x88016000 PA:0x88016000 size:0x1000 MEM-RO-XN-S ... [LV3] VA:0x88020000 PA:0x88020000 size:0x1000 MEM-RW-XN-S Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: If64aa65179ffe223d3e6f1c6bf73a7e4ce7fa536
2020-06-09Merge changes from topic "tegra194-platform-support"Manish Pandey
* changes: tests: arm_arch_svc: introduce support for NVIDIA Denver CPUs Tegra194: introduce per-CPU Hypervisor Timer Interrupt ID Tegra194: skip some timer framework validation tests Tegra194: introduce watchdog timer Tegra194: timers: increase the step value to 5ms Tegra194: create dummy SMMU context for system resume Tegra194: introduce system reset Tegra194: disable some system suspend test cases Tegra194: skip CPU suspend tests requiring SGI as wake source Tegra194: wake: introduce support for RTC as wake source Tegra194: pwr_mgmt: introduce power management support plat: nvidia: introduce platform port for Tegra194 drivers: ti: uart: introduce UART 16550 driver
2020-06-09Update FIP corrupt addressManish V Badarkhe
Updated "FIP_CORRUPT_OFFSET" address which is used to corrupt BL2 in FIP. This address is being changed due to addition of fw-config image in FIP. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I003ccf9ba80b50646ed732b9306e5be757dbf4ff
2020-06-08tests: arm_arch_svc: introduce support for NVIDIA Denver CPUsVarun Wadekar
This patch introduces support for NVIDIA Denver CPUs and variants in the SMCCC_ARCH_WORKAROUND_1 test. Verified with TFTF ARM_ARCH_SVC test on Tegra194. <snip> Running test suite 'ARM_ARCH_SVC' Description: Arm Architecture Service tests > Executing 'SMCCC_ARCH_WORKAROUND_1 test' INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off INFO: Booting INFO: Powering off TEST COMPLETE Passed <snip> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibe179b43fd6a43c4fb5c6cdc7b0c78904efb1b5e
2020-06-08Tegra194: introduce per-CPU Hypervisor Timer Interrupt IDVarun Wadekar
This patch uses PPI 26 as the per-CPU Hypervisor Timer Interrupt ID. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I3e70aec91c129f57b39ca0d1165148880d59c8b3
2020-06-08Tegra194: skip some timer framework validation testsVarun Wadekar
CPUs on Tegra194 platforms cannot be woken up with the RTC timer interrupt after power off. This patch skips the following tests as a result: * Timer framework Validation/Target timer to a power down cpu * Timer framework Validation/Test scenario where multiple CPUs call same timeout * Timer framework Validation/Stress test the timer framework These tests can be enabled once we figure out the right timer source to use for CPU wakeup. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I0f8154e285391fc35fe33428051ab1036ca9c845
2020-06-08Tegra194: introduce watchdog timerVarun Wadekar
This patch adds support for WDT0 that is connected to CPU0 to act as the watchdog timer for Tegra194 platforms. The watchdog timer uses TMR0 as the source and fires if the CPU is hung for more than 10 seconds. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ibe20c1130f86718b919c89436d7f5f49b74d9cc9
2020-06-08Tegra194: timers: increase the step value to 5msVarun Wadekar
The RTC consumes 250us for each register read/write. Increase the step value to 5ms to cover all the register read/write in program_timer(). Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Iac0fc070dbf85a6352fbf147fc5945820e8ee495
2020-06-08Tegra194: create dummy SMMU context for system resumeVarun Wadekar
This patch creates a dummy SMMU context and saves the base address to a pre-negotiated scratch register for the System Resume Firmware to restore. This allows the System Resume Firmware to complete without any errors or warnings. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ic596e6775c6b78ac051ccff02e9574186d6f5335
2020-06-08Tegra194: introduce system resetVarun Wadekar
This patch introduces the flexibility to reset the platform via the SMC_PSCI_SYSTEM_RESET function ID. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I315315f1998d9b9d8f237ac05625328175880922
2020-06-08Tegra194: disable some system suspend test casesVarun Wadekar
This patch disables the following test cases from the PSCI System Suspend Validation test suite: * system suspend from all cores * Suspend system with cores in suspend Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I5f6fcf01ad3b9012fac684f9b3beb87827148de0
2020-06-08Tegra194: skip CPU suspend tests requiring SGI as wake sourceVarun Wadekar
Tegra194 platforms do not support CPU suspend power down and cannot be woken up with an SGI. This patch disables the following tests as a result. + PSCI Affinity Info/Affinity info level0 powerdown + PSCI CPU Suspend/CPU suspend to standby at level 0 + PSCI CPU Suspend/CPU suspend to standby at level 1 + PSCI CPU Suspend/CPU suspend to standby at level 2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I082f254fcd07f9b504f366f2f9a4b41cf7d6bbc3
2020-06-08Tegra194: wake: introduce support for RTC as wake sourceVarun Wadekar
This patch introduces support for adding RTC as a wake source to exit System Suspend state. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ib08d6e2ee7944cd46a91d272ceebffc67b8d7c66
2020-06-08Tegra194: pwr_mgmt: introduce power management supportVarun Wadekar
This patch introduces support to enter the System Suspend power state. The required context is saved to allow the platform to enter and resume from the state. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Iaeaf065f87a2b20981aa92a14fa964802fada20c
2020-06-08plat: nvidia: introduce platform port for Tegra194Varun Wadekar
This patch contains the basic platform support for Tegra194 platforms to initialize the tftf framework and execute tests on the CPUs. The tests require support for a timer, non-volatile memory, UART and GIC. This port uses Tegra_TMR0 as the timer, TI UART 16550 as the console and DRAM as NVM. The GIC driver provided by ARM is used as is. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I2da2121cb05445f47b7d3083cdd6ac6d52586797
2020-06-08drivers: ti: uart: introduce UART 16550 driverVarun Wadekar
This patch introduces a console driver for the TI UART 16550 device. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I46c1abacfe3c2392aee68f0f94b98a284568ddd8
2020-06-08Merge "Add .editorconfig from TF-A"Mark Dykes
2020-06-04TFTF: get FVP platform's topology from build optionsAlexei Fedorov
This patch extends passing FVP topology parameters with FVP_CLUSTER_COUNT and FVP_MAX_CPUS_PER_CLUSTER build options to match TF-A. The change adds more test options, make FVP platform configuration more flexible and eliminates test errors when the platform is configured with number of CPUs less than default values in the makefile. These build options are documented in 'Arm FVP Platform Specific Build Options' section of 'build-options.rst' document. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I01c6437d468885755a5415804b3688e4c878170d
2020-06-03Merge changes from topic "jb/8.6-features"Manish Pandey
* changes: Test that TF-A supports ARMv8.6-ECV Test that TF-A supports ARMv8.6-FGT
2020-06-03Test that TF-A supports ARMv8.6-ECVJimmy Brisson
Note: This test will cause an unhandled exception in the case that TF-A is not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware supports it. Change-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-06-03Add .editorconfig from TF-AJimmy Brisson
This will configure many editors to follow the code style we use. Change-Id: I764485913adf3e93dcbb89cb859ec9350e5f4791 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-06-02Merge "Bug fix in Multicore IRQ spurious test."Manish Pandey
2020-05-29Test that TF-A supports ARMv8.6-FGTJimmy Brisson
Note: This test will cause an unhandled exception in the case that TF-A is not doing its job and enabling ARMv8.6-FGT when the hardware supports it. Change-Id: Iae0fe39895909248b5e7b07a1a73f7702adce7dd Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-05-28Bug fix in Multicore IRQ spurious test.Madhukar Pappireddy
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: Iaf160c8bc9c5807fc9263f5250c0aeedc20e5a8a
2020-05-26Merge changes from topic "spci_to_ffa"Olivier Deprez
* changes: cactus: update memory/device region nodes in manifest cactus: map memory regions, used as RX/TX buffers in SPM SPCI is now called PSA FF-A
2020-05-20cactus: update memory/device region nodes in manifestManish Pandey
add memory/device region nodes in partition manifest to test SPM functionality, memory region has 3 entries(RX, TX and a dummy) while device regions has single dummy entry. RX/TX entries reference to the memory regions through phandle. Memory regions are mapped with following Attributes, RX buffer: read-only TX buffer: read-write dummy: read-write-execute Device region mapped with read-write attribute. Refer to "psa-ffa-manifest-binding.rst" in TF-A project for details about encoding of attributes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1937d99b9ed54e0a578f353d1a44983b9edd5ec0